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full speed usb, 16 kb flash mcu family c8051f326/7 rev. 1.1 8/08 copyright ? 2008 by silicon laboratories c8051f326/7 usb function controller - usb specification 2.0 compliant - full speed (12 mbps) or low speed (1.5 mbps) ope ration - integrated clock recovery; no external crystal required for full speed or low speed - supports three fixed-function endpoints - 256 byte usb buffer memory - integrated transceiver; no external resistors required on-chip debug - on-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required) - provides breakpoints, single stepping, inspect/modify memory and registers - superior performance to emulation systems using ice-chips, target pods, and sockets voltage supply input: 2.7 to 5.25 v - voltages from 3.6 to 5.25 v supported using on -chip voltage regulator high-speed 8051 c core - pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - up to 25 mips throughput with 25 mhz clock - expanded interrupt handler memory - 1536 bytes internal ram (1 k + 256 + 256 usb fifo) - 16k bytes flash; in-system programmable in 512-byte sectors digital peripherals - 15 port i/o; all 5 v tolerant with high sink current - enhanced uart - two general purpose 16-bit timers clock sources - internal oscillator: 0. 25% accuracy with clock recovery enabled. supports all usb and uart modes - external cmos clock - can switch between clock s ources on-the-fly; useful in power saving strategies packages - 28-pin qfn - temperature range: ?40 to +85 c analog peripherals 16 kb isp flash 1536 b sram por debug circuitry 8 interrupts 8051 cpu (25mips) digital i/o precision internal oscillator high-speed controller core usb controller / transceiver vreg port 0 port 2 port 3 uart timer 0 timer 1 low frequency oscillator
c8051f326/7 2 rev. 1.1
rev. 1.1 3 c8051f326/7 table of contents 1. system overview............ ............................................................................. ........... 13 1.1. cip-51? microcontroller core.. ............................................................. ........... 17 1.1.1. fully 8051 compatible...... ............................................................. ........... 17 1.1.2. improved throughput ............ ........................................................ ........... 17 1.1.3. additional features .......... ............................................................. ........... 18 1.2. on-chip memory......... ........................................................................... ........... 19 1.3. universal serial bus controll er ................. ............................................. ........... 20 1.4. voltage regulator ....... ........................................................................... ........... 20 1.5. on-chip debug circuitr y.................... .................................................. ............. 21 1.6. programmable digital i/o........ ............................................................... ........... 22 1.7. serial ports ............ ................................................................................ ........... 22 2. absolute maximum ratings ........ ............................................................... ........... 23 3. global dc electrical characteristi cs ...................... ................................. ............. 24 4. pinout and package definitions..... ............... ............................................. ........... 25 5. voltage regulator (reg0)......... .................................................................. ........... 31 5.1. regulator mode selectio n................ ........................................................ ......... 31 5.2. vbus detection .......... ........................................................................... ........... 31 6. cip-51 microcontroller ............. .................................................................. ........... 35 6.1. instruction set ........... ............................................................................. ........... 36 6.1.1. instruction and cpu timing .. ........................................................ ........... 36 6.1.2. movx instruction and program memory ... ................................. ............. 37 6.2. memory organization........... .................................................................. ........... 41 6.2.1. program memory.............. ............................................................. ........... 41 6.2.2. data memory........ ......................................................................... ........... 42 6.2.3. general purpose registers ........................................................... ........... 42 6.2.4. bit addressable lo cations.............. ............................................... ........... 42 6.2.5. stack ................. ........................................................................... ........... 42 6.2.6. special function registers. ........................................................... ........... 43 6.2.7. register descriptions ....... ............................................................. ........... 45 6.3. interrupt handler ................ .................................................................. ............. 48 6.3.1. mcu interrupt sources a nd vectors ............ ................................. ........... 48 6.3.2. external interrupts .......... ............................................................... ........... 49 6.3.3. interrupt priorities ........ .................................................................. ........... 49 6.3.4. interrupt latency .............. ............................................................. ........... 49 6.3.5. interrupt register descrip tions .............. .......................................... ......... 50 6.4. power management modes ........... ........................................................ ........... 55 6.4.1. idle mode............ ........................................................................... ........... 55 6.4.2. stop mode ...................... ............................................................... ........... 55 7. reset sources .......... .................................................................................. ........... 57 7.1. power-on reset .................. .................................................................. ........... 58 7.2. power-fail reset / vdd monito r............................................................ ........... 59 7.3. external reset .......... ............................................................................. ........... 60 7.4. missing clock dete ctor reset................. ............................................... ........... 60
c8051f326/7 4 rev. 1.1 7.5. flash error reset...... ............................................................................. ........... 60 7.6. software reset ......... ............................................................................. ........... 60 7.7. usb reset ................ ............................................................................. ........... 60 8. flash memory .......... .................................................................................. ........... 63 8.1. programming the flash memory .. ........................................................ ........... 63 8.1.1. flash lock and key function s ................ .............. ............... ........... ......... 63 8.1.2. flash erase procedur e................................................................ ............. 63 8.1.3. flash write procedu re............... .................................................. ............. 64 8.2. non-volatile data storage.... .................................................................. ........... 65 8.3. security options................. .................................................................. ............. 65 9. external ram ........... .................................................................................. ........... 69 9.1. accessing user xram.. ......................................................................... ........... 69 9.2. accessing usb fifo space..... ............................................................. ........... 70 10. oscillators ................ .................................................................................. ............. 71 10.1.programmable internal oscilla tor .................... .............. ............... ........... ......... 71 10.1.1.adjusting the internal oscillator on c8051f326/7 de vices......... ............. 72 10.1.2.internal oscillator susp end mode ................ ................................. ........... 72 10.2.internal low-frequency (l-f) o scillator ............... ................................. ........... 74 10.3.cmos external clock input............. ........................................................ ......... 74 10.4.4x clock multiplier .... ............................................................................. ........... 75 10.5.system and usb clock selection ............ ............................................. ........... 76 10.5.1.system clock selection ... ............................................................. ........... 76 10.5.2.usb clock selection ........ ............................................................. ........... 76 11. port input/output ....... ................................................................................ ........... 79 11.1.port i/o initialization ........ ...................................................................... ........... 81 11.2.general purpose port i/o .... .................................................................. ........... 81 12. universal serial bus controller (usb0)........... .......................................... ........... 87 12.1.endpoint addressing .... ......................................................................... ........... 88 12.2.usb transceiver ................. .................................................................. ........... 88 12.3.usb register access .......... .................................................................. ........... 90 12.4.usb clock configuration........ ............................................................... ........... 94 12.5.fifo management .......... ...................................................................... ........... 95 12.5.1.fifo split m ode .................... ........................................................ ........... 95 12.5.2.fifo double buffering ....... ........................................................... ........... 95 12.5.3.fifo access ........ ......................................................................... ........... 96 12.6.function addressing............ .................................................................. ........... 97 12.7.function configuration and cont rol......................................................... ......... 98 12.8.interrupts ........... .................................................................................. ........... 101 12.9.the serial interface engine . .................................................................. ......... 104 12.10. endpoint0.......... .................................................................................. ......... 104 12.10.1.endpoint0 setup transacti ons .............. ................................. ........... 104 12.10.2.endpoint0 in transactions... ................. .............. ............... .................. 105 12.10.3.endpoint0 out tran sactions................ .............. ............... .................. 105 12.11.configuring endpoint1 ... ...................................................................... ......... 108
rev. 1.1 5 c8051f326/7 12.12.controlling endpoint1 in......... ............................................................. ......... 108 12.12.1.endpoint1 in interrupt or bulk mode.......... ................................. ......... 108 12.12.2.endpoint1 in isoc hronous mode.............. ................................. ........... 108 12.13.controlling endpoint1 out..... ............................................................. ......... 112 12.13.1.endpoint1 out interrupt or bulk mode........ ............................... ......... 112 12.13.2.endpoint1 out isochronous mode............................................. ......... 112 13. uart0................ ........................................................................................... ......... 117 13.1.baud rate generator ............. ............................................................... ......... 118 13.2.data format......... .................................................................................. ......... 120 13.3.configuration and operat ion ................ ................................................. ......... 121 13.3.1.data transmission ........... ............................................................. ......... 121 13.3.2.data reception .... ......................................................................... ......... 121 13.3.3.multiprocessor communicati ons ................................................... ......... 122 14. timers ................... .................................................................................. .............. 12 7 14.1.timer 0 and time r 1 operating modes........ .......................................... ......... 127 14.1.1.mode 0: 13-bit timer ........ ............................................................. ......... 128 14.1.2.mode 1: 16-bit timer ........ ............................................................. ......... 129 14.1.3.mode 2: 8-bit timer with auto-reload .......... ................................. ......... 129 14.1.4.mode 3: two 8-bit timers (timer 0 only) ................ ............ .................. 130 15. c2 interface ................ .................................................................................. ......... 135 15.1.c2 interface registers......... .................................................................. ......... 135 15.2.c2 pin sharing ......... ............................................................................. ......... 137 document change list............... ...................................................................... ........ 138 contact information.......... ................................................................................ ........ 140
c8051f326/7 6 rev. 1.1
rev. 1.1 7 c8051f326/7 list of figures 1. system overview figure 1.1. c8051f326 block diagr am ...................... ................................. ............. 14 figure 1.2. c8051f327 block diagr am ...................... ................................. ............. 15 figure 1.3. typical connections for the c8051f326................ ............ ........... ......... 16 figure 1.4. typical connections for the c8051f327................ ............ ........... ......... 16 figure 1.5. comparison of pe ak mcu execution speeds ......... ................. ............. 17 figure 1.6. on-chip clock and rese t ........................................................... ........... 18 figure 1.7. on-board memory ma p.................. ............................................. ........... 19 figure 1.8. usb controll er block diagram.......... .......................................... ........... 20 figure 1.9. development/in-syst em debug diagram................. ................. ............. 21 2. absolute maximum ratings 3. global dc electrical characteristics 4. pinout and package definitions figure 4.1. c8051f326 qfn-28 pinout diagram (top view) .... ................. ............. 27 figure 4.2. c8051f327 qfn-28 pinout diagram (top view) .... ................. ............. 28 figure 4.3. qfn-28 package drawin g ................ .......................................... ........... 29 figure 4.4. qfn-28 recomm ended pcb land pattern ............. ................. ............. 30 5. voltage regulator (reg0) figure 5.1. reg0 configuratio n: usb bus-powered ... ................................. ........... 32 figure 5.2. reg0 configuratio n: usb self-powered ............ ............... ........... ......... 32 figure 5.3. reg0 configurat ion: usb self-powered, regulat or disabled .............. 33 figure 5.4. reg0 configuratio n: no usb connection.. ................................ ........... 33 6. cip-51 microcontroller figure 6.1. cip-51 block diagram.. ............................................................... ........... 35 figure 6.2. memory map ........... .................................................................. ............. 41 7. reset sources figure 7.1. reset sources......... .................................................................. ............. 57 figure 7.2. power-on and vdd monitor reset timing ....... ............................ ......... 58 8. flash memory figure 8.1. flash program me mory map and security byte .... ............ ........... ......... 66 9. external ram figure 9.1. external ram memory map .................. .............. ............... ........... ......... 69 figure 9.2. xram memory m ap expanded view......... ................................. ........... 70 10. oscillators figure 10.1. oscillator diagram............... ........................................................ ......... 71 11. port input/output figure 11.1. port i/o functional block diagram ................ ............................ ........... 79 figure 11.2. port i/o ce ll block diagram ............ .......................................... ........... 80 12. universal serial bus controller (usb0) figure 12.1. usb0 block diagram................ ................................................. ........... 87 figure 12.2. usb0 regi ster access scheme........ .......................................... ......... 90 figure 12.3. usb fifo al location ............. .................................................. ............. 95 13. uart0 figure 13.1. uart0 block diagram ............. ................................................. ......... 117
c8051f326/7 8 rev. 1.1 figure 13.2. uart0 timing without parity or extra bit..... ............................ ......... 120 figure 13.3. uart0 timing with parity ....... ................................................. ......... 120 figure 13.4. uart0 timing with extra bit .......... .......................................... ......... 120 figure 13.5. typical uart inte rconnect diagram.................... ............ .................. 121 figure 13.6. uart multi-proc essor mode interconne ct diagram .......... ................ 122 14. timers figure 14.1. t0 mode 0 bl ock diagram............... .......................................... ......... 128 figure 14.2. t0 mode 2 bl ock diagram............... .......................................... ......... 129 figure 14.3. t0 mode 3 bl ock diagram............... .......................................... ......... 130 15. c2 interface figure 15.1. typical c2 pin sharing.......... .................................................. ........... 137
rev. 1.1 9 c8051f326/7 list of tables 1. system overview table 1.1. product select ion guide ................. ............................................. ........... 13 2. absolute maximum ratings table 2.1. absolute maximum rati ngs ................... .............. ............... ........... ......... 23 3. global dc electrical characteristics table 3.1. global dc electrical characteristics ........... ................................. ........... 24 4. pinout and package definitions table 4.1. pin definitions for the c8051f326/7 ......... ................................. ............. 25 table 4.2. qfn-28 package dimensions ........... .......................................... ........... 29 table 4.3. qfn-28 pcb land patt ern dimesions ....... ................................. ........... 30 5. voltage regulator (reg0) table 5.1. voltage regulat or electrical specificat ions . . . . . . . . . . . . . . . . . . . . . 31 6. cip-51 microcontroller table 6.1. cip-51 instruction se t summary .............. ................................. ............. 37 table 6.2. special function regi ster (sfr) memory map ...... ............ ........... ......... 43 table 6.3. special functi on registers ................ .......................................... ........... 43 table 6.4. tmod.3 contro l of /int0 ......... .................................................. ............. 49 table 6.5. interrupt summ ary ................. ........................................................ ......... 50 7. reset sources table 7.1. reset electrical charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8. flash memory table 8.1. flash electric al characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9. external ram 10. oscillators table 10.1. typical usb full s peed clock settings .... ................................. ........... 76 table 10.2. typical usb low spee d clock settings .... ................................ ........... 76 table 10.3. internal osc illator electrical characte ristics . . . . . . . . . . . . . . . . . . . . 78 11. port input/output table 11.1. port i/o dc elec trical characteristics (c8051f326) . . . . . . . . . . . . . 85 table 11.2. port i/o dc elec trical characteristics (c8051f327) . . . . . . . . . . . . . 85 12. universal serial bus controller (usb0) table 12.1. endpoint addr essing scheme ............. .............. ............... ........... ......... 88 table 12.2. usb0 c ontroller registers ......... ............................................... ........... 93 table 12.3. fifo configur ations .............. .................................................. ............. 95 table 12.4. usb transcei ver electrical characteristics . . . . . . . . . . . . . . . . . . . 115 13. uart0 table 13.1. baud rate generator settings for st andard baud rates ................... 119 14. timers table 14.1. timer modes .. ................. ........................................................... ......... 127 table 14.2. timer 0 operation .... .................................................................. ......... 128 15. c2 interface
c8051f326/7 10 rev. 1.1
rev. 1.1 11 c8051f326/7 list of registers sfr definition 5.1. reg0cn : voltage regulator control . . . . . . . . . . . . . . . . . . . . . . 34 sfr definition 6.1. dpl: da ta pointer low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 sfr definition 6.2. dph: data pointer high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 sfr definition 6.3. sp: stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 sfr definition 6.4. psw: pr ogram status word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 sfr definition 6.5. acc: accu mulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 sfr definition 6.6. b: b register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 sfr definition 6.7. ie: interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 sfr definition 6.8. ip: interr upt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 sfr definition 6.9. eie1: extended interrupt enable 1 . . . . . . . . . . . . . . . . . . . . . . . . 53 sfr definition 6.10. eip1: extended inte rrupt priority 1 . . . . . . . . . . . . . . . . . . . . . . . 53 sfr definition 6.11. eie2: extended interrupt enable 2 . . . . . . . . . . . . . . . . . . . . . . . 53 sfr definition 6.12. eip2: extended inte rrupt priority 2 . . . . . . . . . . . . . . . . . . . . . . . 54 sfr definition 6.13. pc on: power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 sfr definition 7.1. vdm0cn : vdd monitor control . . . . . . . . . . . . . . . . . . . . . . . . . . 59 sfr definition 7.2. rstsrc: reset source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 sfr definition 8.1. psctl: program store r/w contro l . . . . . . . . . . . . . . . . . . . . . . . 66 sfr definition 8.2. flkey: flash lock and key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 sfr definition 8.3. flscl: fl ash scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 sfr definition 9.1. emi0cn: exter nal memory interface control . . . . . . . . . . . . . . . . 70 sfr definition 10.1. oscicn: internal oscillator control . . . . . . . . . . . . . . . . . . . . . . 72 sfr definition 10.2. oscicl : internal oscillator ca libration . . . . . . . . . . . . . . . . . . . . 73 sfr definition 10.3. osclcn: inter nal l-f oscillator control . . . . . . . . . . . . . . . . . . . 74 sfr definition 10.4. clkmul : clock multiplier control . . . . . . . . . . . . . . . . . . . . . . . . 75 sfr definition 10.5. clksel: clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 sfr definition 11.1. gpiocn: global port i/o c ontrol . . . . . . . . . . . . . . . . . . . . . . . . 82 sfr definition 11.2. p0: port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 sfr definition 11.3. p0mdout: port 0 output mode . . . . . . . . . . . . . . . . . . . . . . . . . . 82 sfr definition 11.4. p2: port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 sfr definition 11.5. p2mdout: port 2 output mode . . . . . . . . . . . . . . . . . . . . . . . . . . 83 sfr definition 11.6. p3: port3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 sfr definition 11.7. p3mdout: port 3 output mode . . . . . . . . . . . . . . . . . . . . . . . . . . 84 usb register definition 12.1. usb0xcn: usb0 transceiver c ontrol . . . . . . . . . . . . . 89 usb register definition 12. 2. usb0adr: usb0 indi rect address . . . . . . . . . . . . . . . . 91 usb register definiti on 12.3. usb0dat: usb0 data . . . . . . . . . . . . . . . . . . . . . . . . . 92 usb register definition 12. 4. index: usb0 endpoint index . . . . . . . . . . . . . . . . . . . . 92 usb register definition 12. 5. clkrec: clock recovery control . . . . . . . . . . . . . . . . 94 usb register definition 12.6. fifon: usb0 endpoint fifo a ccess . . . . . . . . . . . . . . 96 usb register definition 12.7. faddr: usb0 function address . . . . . . . . . . . . . . . . . 97 usb register definition 12. 8. power: usb0 power . . . . . . . . . . . . . . . . . . . . . . . . . 99 usb register definition 12.9. framel: usb0 frame number low . . . . . . . . . . . . . 100 usb register definiti on 12.10. frameh: usb0 frame number high . . . . . . . . . . . 100 usb register definition 12.11. in1int: usb0 in endpoint interrupt . . . . . . . . . . . . . 101
c8051f326/7 12 rev. 1.1 usb register definition 12.12. out1int: usb0 ou t endpoint interrupt . . . . . . . . . . 101 usb register definition 12.13. cmint: usb0 common interrupt . . . . . . . . . . . . . . . 102 usb register definition 12.14. in1ie: usb0 in endpoint interrupt enab le . . . . . . . . 102 usb register definiti on 12.15. out1ie: usb0 out endpoint interrupt enable . . . . . 103 usb register definition 12.16. cmie: usb0 comm on interrupt enable . . . . . . . . . . 103 usb register definition 12.17. e0csr: usb0 endpoi nt0 control . . . . . . . . . . . . . . . 106 usb register definition 12.18. e0cnt: usb0 endpoint 0 data count . . . . . . . . . . . 107 usb register definiti on 12.19. eincsrl: usb0 in endpoi nt control low byte . . . . 110 usb register definiti on 12.20. eincsrh: usb0 in endpoi nt control high byte . . . 111 usb register defini tion 12.21. eoutcsrl: usb0 out endpoint control low byte 113 usb register definition 12. 22. eoutcsrh: usb0 out endpoint control high byte . . . . . . . . . . . . . . . . . . . . 114 usb register definiti on 12.23. eoutcntl: usb0 out e ndpoint count low . . . . . 114 usb register defini tion 12.24. eoutcnth: usb0 out endpoint count high . . . . 114 sfr definition 13.1. scon0: uart0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 sfr definition 13.2. smod0: uart0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 sfr definition 13.3. sbuf0: uart0 data buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 sfr definition 13.4. sbcon0: ua rt0 baud rate generator cont rol . . . . . . . . . . . 125 sfr definition 13.5. sbrlh0: uart0 baud rate generator high byte . . . . . . . . . . 126 sfr definition 13.6. sbrll0: ua rt0 baud rate generator low by te . . . . . . . . . . . 126 sfr definition 14.1. tcon: timer cont rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 sfr definition 14.2. tmod: ti mer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 sfr definition 14.3. ckcon: clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 sfr definition 14.4. tl0: timer 0 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 sfr definition 14.5. tl1: timer 1 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 sfr definition 14.6. th0: timer 0 hi gh byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 sfr definition 14.7. th1: timer 1 hi gh byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 c2 register definition 15.1. c2add: c2 address . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 c2 register definition 15.2. device id: c2 device id . . . . . . . . . . . . . . . . . . . . . . . . 135 c2 register definition 15.3. revid: c2 revision id . . . . . . . . . . . . . . . . . . . . . . . . . 136 c2 register definition 15.4. fp ctl: c2 flash programming cont rol . . . . . . . . . . . . 136 c2 register definition 15.5. fp dat: c2 flash programming data . . . . . . . . . . . . . . 136
rev. 1.1 13 c8051f326/7 1. system overview c8051f326/7 devices are fully integr ated mixed-signal system-on-a-chip mcus. highlighted features are listed below. refer to ta b l e 1.1 for specific product feature selection. ? high-speed pipelined 8051-compatible microcontroller core (up to 25 mips) ? in-system, full-speed, non-intrusive debug interface (on-chip) ? universal serial bus (usb) function controller with th ree fixed-function endpoint pipes, integrated trans - ceiver, and 256b fifo ram ? supply voltage regulator ? precision programmable 12 mhz internal oscillator and 4x clock multiplier ? 16k kb of on-chip flash memory ? 1536 total bytes of on-chip ram (256 + 1 k + 256 usb fifo) ? enhanced uart, serial interfaces implemented in hardware ? two general-purpose 16-bit timers ? on-chip power-on reset, vdd monitor, and missing clock detector ? 15 port i/o (5 v tolerant) with on-chip power-on reset, vdd monitor , voltage regula tor, and clock oscillato r, c8051f326/7 devices are truly stand-alone system-on-a-chip solutions. the flash memory can be reprogrammed in-circuit, pro - viding non-volatile data storage, and also allowing fi eld upgrades of the 8051 firmware. user software has complete control of all peripherals, and may individua lly shut down any or all peripherals for power sav - ings. the on-chip silicon laboratories 2-wi re (c 2) development in terface allows non-intr usive (uses no on-chip resources), full speed, in-circuit debugging using the production mcu installed in the final application. this debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. all analog and digita l peripherals are fully functional while debugging using c2. the two c2 interface pins can be shared with user functions , allowing in-system debugging with - out occupying package pins. each device is specified for 2.7?5.25 v operation over the industrial temperature range (?40 to +85 c). fo r voltages above 3.6 v, the on-chip voltage regulator must be u sed. a minimum of 3.0 v is required for usb communication. the port i/o and rst pins are tolerant of input signals up to 5 v. c8051f326/7 are a vailable in two 28-pin qfn packages with different pinouts. the rohs compliant devices are marked with a -gm suffix in the part number. the port i/o on c8051f326 devices is powered from a separate i/o supply allowing it to interface to low voltage logic. table 1.1. product selection guide ordering part number mips (peak) flash memory ram calibrated internal oscillator usb supply voltage regulator uart timers (16-bit) digital port i/os separate i/o supply package c8051f326-gm 25 16k 1536 3 3 3 3 2 15 3 qfn-28 C8051F327-GM 25 16k 1536 3 3 3 3 2 15 ? qfn-28
c8051f326/7 14 rev. 1.1 figure 1.1. c8051f326 block diagram uart 16 kb flash 256 byte sram por sfr bus 8 0 5 1 c o r e reset /rst/c2ck debug hw brown- out p 0 d r v 1 kb xram xtal2 p0.0/sysclk p0.1 p0.2 p0.3/xtal2 p0.4/tx p0.5/rx p0.6 p0.7 regin port 0 latch timer 0,1 system clock p 2 d r v p 3 d r v p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p3.0/c2d c2d port 2 latch port 3 latch usb controller usb transceiver analog/digital power voltage regulator 5.0 v 256 byte usb sram vbus d+ d- 12 mhz internal oscillator gnd vdd in out enable x4 2 usb clock 2 clock recovery /sysclk low freq oscillator xtal2 1,2,3,4 vio
rev. 1.1 15 c8051f326/7 figure 1.2. c8051f327 block diagram uart 16 kb flash 256 byte sram por sfr bus 8 0 5 1 c o r e reset /rst/c2ck debug hw brown- out p 0 d r v 1 kb xram xtal2 p0.0/sysclk p0.1 p0.2 p0.3/xtal2 p0.4/tx p0.5/rx p0.6 p0.7 regin port 0 latch timer 0,1 system clock p 2 d r v p 3 d r v p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p3.0/c2d c2d port 2 latch port 3 latch usb controller usb transceiver analog/digital power voltage regulator 5.0 v 256 byte usb sram vbus d+ d- 12 mhz internal oscillator gnd vdd in out enable x4 2 usb clock 2 clock recovery /sysclk low freq oscillator xtal2 1,2,3,4
c8051f326/7 16 rev. 1.1 figure 1.3. typical conn ections for the c8051f326 figure 1.4. typical conn ections for the c8051f327
rev. 1.1 17 c8051f326/7 1.1. cip-51? microcontroller core 1.1.1. fully 8051 compatible the c8051f326/7 family utilizes silicon laboratories' proprietary cip-51 microcontroller core. the cip-51 is fully compatible with the mcs- 51? instruction set; standard 803x/805x assemblers and compilers can be used to develop software. the cip-51 core offers all the peripherals included with a standard 8052, including two 16-bit counter/time rs, a full-duplex uart with extended baud rate configuration, 1536 bytes o f on-chip ram, 128 byte special function register (sfr) address space, and 15 i/o pins. 1.1.2. improved throughput the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan - dard 8051 architecture. in a standar d 8051, all inst ructions except for mul and div take 12 or 24 system clock cycles to execute with a ma ximum system clock of 12-to-24 mhz. by contrast, the cip-51 core exe - cutes 70% of its instructions in one or two system clock cy cles, with only four inst ructions taking more than four system clock cycles. the cip-51 has a total of 109 instructions. the table be low shows the total number of instructions that require each execution time. with the cip-51's maximum system clock at 25 mhz, it has a peak throughput of 25 mips. figure 1.5 shows a comparison of peak throughputs for variou s 8 -bit microcontroller cores with their maximum sys - tem clocks. figure 1.5. comparison of peak mcu execution speeds clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1 5 10 15 20 aduc812 8051 (16 mhz clk) philips 80c51 (33 mhz clk) microchip pic17c75x (33 mhz clk) silicon labs cip-51 (25 mhz clk) mips 25
c8051f326/7 18 rev. 1.1 1.1.3. additional features the c8051f326/7 soc family includes several key enhancements to the cip-51 core and peripherals to improve performance and ease of use in end applications. the extended interrupt handler provides 8 interrupt sources into the cip-51. an inte rrupt driven system requires less intervention by the mcu, giving it more effective throughput. the interrupt sources are very useful when building multi-ta sking, real-time systems. seven reset sources are available: power-on reset circuitry (por), an on-chip vdd monitor (forces reset whe n power supply voltage drops below v rst as given in table 7.1 on page 62 ), the usb controller (usb bus reset or a vbus transition), a missing clock detector , a forced software reset, an external reset pin, and an errant flash read/write protection circuit. each reset source except for the por, reset input pin, or flash error may be disabled by the user in software. the internal oscillator is factory calibrated to 12 mhz 1.5%, and the internal oscillator period may be user programmed in ~0.25% increments. an additional low-frequency oscilla tor is also available which facili - tates low power operation. a clock recovery mechanism allows the internal oscillator to be used with the 4x clock multiplier as the usb clock sour ce in full speed mode; the internal oscillator can also be used as the usb clock source in low speed mode. an extern al cmos clock may also be used with the 4x clock multiplier. the system clock may be configured to use the internal osc illator, external cl ock, low-frequency oscillator, or the clock multiplier outpu t divided by 2. if desired, the system clock source may be switched on-the-fly between oscillator source s. the external clock and internal low-freque ncy oscillator can be extremely useful in low power applications, allowing the mcu to run from a slow (power saving) clock source, while periodically s witching to the high-frequency internal oscillator as needed. figure 1.6. on-chi p clock and reset missing clock detector (one- shot) (software reset) system reset reset funnel en swrsf internal oscillator system clock cip-51 microcontroller core extended interrupt handler clock select mcd enable xtal2 external clock input errant flash operation /rst (wired-or) power on reset + - vdd supply monitor enable '0' low frequency oscillator
rev. 1.1 19 c8051f326/7 1.2. on-chip memory the cip-51 has a standard 8051 program and data addr ess configuration. it in cludes 256 bytes of data ram, with the upper 128 bytes dual-mapped. indirect addressing accesses the upper 128 bytes of general purpose ram, and direct addressing accesses the 128 byte sfr addre ss space. the lower 128 bytes of ram are accessible via direct and indirect addressing. the first 32 bytes are addressable as four banks of general purpose registers, and the next 16 byte s can be byte addressable or bit addressable. program memory consists of 16k bytes of flash. this memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip programming voltage. see figure 1.7 for the mcu system memory map. figure 1.7. on-board memory map same 1024 bytes as from 0x0000 to 0x03ff, wrapped on 1k-byte boundaries program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 1024 bytes (accessable using movx instruction) 0x0000 0x03ff 0x0400 0xffff 16k flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0x3e00 0x3dff usb fifos 256 bytes accessible through usb registers only 0x3fff
c8051f326/7 20 rev. 1.1 1.3. universal serial bus controller the universal serial bus controller (usb0) is a usb 2.0 peripheral wi th integrated transceiver and end - point fifo ram. the controller supports both full and low spee d modes. a total of three endpoint pipes are available: a bi-directional control endpoint (endpoin t0) and a data endpoint (endpoint1) with one in pipe and one out pipe. a 256 block of xram is used as dedicated usb fifo space. this fifo space is distributed between end point0 and endpoint1. endpoint0 is 64 bytes, and endpoint1 has a 64 byte in pipe and a 128 byte out pipe. usb0 can be operated as a full or low speed functi on. th e on-chip 4x clock multiplier and clock recovery circuitry allow both full a nd low speed options to be implemented with the on-chi p precision oscillator as the usb clock source. an external clock source can also be used with the 4x clock multiplier to generate the usb clock. the usb transceiver is usb 2.0 compliant, and incl ude s on-chip matching and pullup resistors. the pul - lup resistors can be enabled/disabled in sof tware, and will ap pear on the d+ or d? pin according to the software-selected speed setting (full or low speed). figure 1.8. usb contro ller block diagram 1.4. voltage regulator c8051f326/7 devices include a voltage regulator (reg0). when enabled, the reg0 output appears on the vdd pin and can be used to power external devi ces. reg0 can be enabled/disabled by software. transceiver serial interface engine (sie) usb fifos (256b ram) d+ d- vdd endpoint0 in/out endpoint1 in out data transfer control cip-51 core usb control, status, and interrupt registers
rev. 1.1 21 c8051f326/7 1.5. on-chip debug circuitry c8051f326/7 devices include on-chip silicon laboratories 2-wire (c2) debug circuitry that provides non- intrusive, full speed, in-circuit debugging of the production part installed in the end application. the silicon laboratorie s' debugging sys tem supports inspection and modification of memory and registers, breakpoints, and single stepping. no additional target ram, program memory, timers, or communications channels are required. all the digital and analog peri pherals are functional and work correctly while debug - ging. all the peripherals (except for the usb) are stalle d when the mcu is halted, during single stepping, or at a breakpoint in order to keep them synchronized. the c8051f326dk development kit provides all the har dwar e and software necessary to develop applica - tion code and perform in-circuit debugging with th e c8051f326/7 mcus. the kit includes a windows development environment, a serial adapter for connecti ng to the c2 port, and a target application board. all of the necessary communication cables and a wa ll-mount power supply are also supplied with the development kit. the silicon laboratories debug environment is a vastly superior configuration for devel - oping and debugging embedded applications compared to standard mcu emulators, which use on-board "ice chips" and target cables and require the mcu in the application board to be socke ted. the silicon laboratories debug environment enhances ease of use and preserves the performance of on-chip periph - erals. figure 1.9. development/in -system debug diagram target pcb serial adapter vdd gnd c2 (x2), vdd, gnd windows pc silicon laboratories integrated development environment c8051f326
c8051f326/7 22 rev. 1.1 1.6. programmable digital i/o c8051f326/7 devices include 15 i/o pins (one byte -wide port, one 6-bit-wide and one 1-bit-wide port). the c8051f326/7 ports behave like typical 8051 port s with a few enhancements. each port pin may be configured as a digital input or output pin. pins selected as digital outputs may additionally be configured for push-pull or open-drain output. the ?weak pullups? that are fixed on typical 8051 devices may be glob - ally disabled, pr oviding pow er savings capabilities. 1.7. serial ports the c8051f326/7 family includes a full-duplex uart with enhanced baud rate configuration. the serial interface is fully implemented in ha rdware and makes extensive use of t he cip-51's interrupts, thus requir - ing very little cpu intervention.
rev. 1.1 23 c8051f326/7 2. absolute maximum ratings table 2.1. absolute maximum ratings parameter conditions min typ max units ambient temperature under bias ?55 ? 125 c storage temperature ?65 ? 150 c voltage on any port i/o pin or rst with respect to gnd ?0.3 ? 5.8 v voltage on vdd or vio with respect to gnd ?0.3 ? 4.2 v maximum total current through vdd, vio, and gnd ??500ma maximum output current sunk by rst or any port pin ??100ma note: stresses above those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation list ings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
c8051f326/7 24 rev. 1.1 3. global dc electrical characteristics table 3.1. global dc electrical characteristics ?40 to +85 c, 25 mhz system clock unless otherwise specified. parameter conditions min typ max units i/o supply voltage (vio) 1,2 1.8 3.3 3.6 v core supply voltage (vdd) 3 2.7 3.3 3.6 v core supply current with cpu active vdd = 3.3 v, clock = 24 mhz vdd = 3.3 v, clock = 3 mhz vdd = 3.3 v, clock = 32 khz ? ? ? 11 1.9 20 ? ? ? ma ma a core supply current with cpu inactive (not accessing flash) vdd = 3.3 v, clock = 24 mhz vdd = 3.3 v, clock = 3 mhz vdd = 3.3 v, clock = 32 khz ? ? ? 4.4 0.83 13 ? ? ? ma ma a digital supply current (sus- pend mode or shutdown mode) oscillator not running ?< 0.1? a digital supply ram data reten- tion voltage ?1.5? v sysclk (system clock) 4 0 ? 25 mhz t sysh (sysclk high time) 18 ?? ns t sysl (sysclk low time) 18 ?? ns specified operating tempera- ture range ?40 ? +85 c notes: 1. th e i/o supply voltage (vio) must be less than or equal to the core supply voltage (vdd). 2. fo r c8051f327 devices, vio is internally connected to vdd. 3. usb r equires 3.0 v minimum core supply voltage (vdd). 4. sysclk mu st be at least 32 khz to enable debugging.
rev. 1.1 25 c8051f326/7 4. pinout and package definitions table 4.1. pin definitions for the c8051f326/7 name pin numbers type description ?f326 ?f327 vdd 6 6 power in power out 2.7?3.6 v core supply voltage input. 3.3 v voltage regulator output. see section 5. vio 5 ? power in v i/o supply voltage input. the voltage at this pin must be less th an or equal to the core supply voltage (v dd ) for the 'f326. on the 'f327, this pin is internally connected to v dd . gnd 2 3 ground. rst / c2ck 9 9 d i/o d i/o device reset. open-drain output of internal por or vdd m onitor. an external source can initiate a system reset by driving this pin low for at least 15 s. see section 7 . clock signal for the c2 debug interf ace. p3.0/ c2d 10 10 d i/o d i/o port 3.0. see section 11 for a complete description. bi-directional data signal for the c2 debug interface. regin 7 7 power in 5 v regulator input. this pin is the input to the on-chip volt - age regulator. vbus 8 8 d in vbus sense input. this pin should be connected to the vbus sign al of a usb network. a 5 v signal on this pin indi - cates a usb network connection. d+ 3 4 d i/o usb d+. d? 4 5 d i/o usb d?. p0.0 1 2 d i/o port 0.0. see section 11 for a complete description. p0.1 28 1 d i/o port 0.1. see section 11 for a complete description. p0.2 27 28 d i/o port 0.2. see section 11 for a complete description. p0.3/ xtal2 26 27 d i/o d in port 0.3. see section 11 for a complete description. external clock input. see section 10 for a complete description. p0.4 25 26 d i/o port 0.4. see section 11 for a complete description. p0.5 24 25 d i/o port 0.5. see section 11 for a complete description.
c8051f326/7 26 rev. 1.1 p0.6 23 24 d i/o port 0.6. see section 11 for a complete description. p0.7 22 23 d i/o port 0.7. see section 11 for a complete description. p2.0 19 19 d i/o port 2.0. see section 11 for a complete description. p2.1 18 18 d i/o port 2.1. see section 11 for a complete description. p2.2 12 12 d i/o port 2.2. see section 11 for a complete description. p2.3 11 11 d i/o port 2.3. see section 11 for a complete description. p2.4 17 17 d i/o port 2.4. see section 11 for a complete description. p2.5 16 16 d i/o port 2.5. see section 11 for a complete description. n.c. pins for the ?f326: 13, 14, 15, 20, and 21. n.c. pins for the ?f327: 13, 14, 15, 20, 21, and 22. table 4.1. pin definitions for the c8051f326 /7 (continued) name pin numbers type description ?f326 ?f327
rev. 1.1 27 c8051f326/7 figure 4.1. c8051f326 qfn-28 pinout diagram (top view) 4 5 6 7 2 1 3 11 12 13 14 9 8 10 18 17 16 15 20 21 19 25 26 27 28 23 22 24 c8051f326 top view p0.0 gnd d+ d- vio vdd regin vbus /rst / c2ck p3.0 / c2d p2.3 p2.2 n.c. n.c. n.c. p2.5 p2.4 p2.1 p2.0 n.c. n.c. p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 gnd
c8051f326/7 28 rev. 1.1 figure 4.2. c8051f327 qfn-28 pinout diagram (top view) 4 5 6 7 2 1 3 11 12 13 14 9 8 10 18 17 16 15 20 21 19 25 26 27 28 23 22 24 c8051f327 top view p0.1 p0.0 gnd d+ d- vdd regin vbus /rst / c2ck p3.0 / c2d p2.3 p2.2 n.c. n.c. n.c. p2.5 p2.4 p2.1 p2.0 n.c. n.c. n.c. p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 gnd
rev. 1.1 29 c8051f326/7 figure 4.3. qfn-28 package drawing table 4.2. qfn-28 package dimensions dimension min typ max dimension min typ max a 0.80 0.90 1.00 l 0.35 0.55 0.65 a1 0.00 0.02 0.05 l1 0.00 ? 0.15 a3 0.25 ref aaa 0.15 b 0.18 0.23 0.30 bbb 0.10 d 5.00 bsc. ddd 0.05 d2 2.90 3.15 3.35 eee 0.08 e 0.50 bsc. z 0.44 e 5.00 bsc. y 0.18 e2 2.90 3.15 3.35 notes: 1. al l dimensions shown are in millim eters (mm) unless otherwise noted. 2. d imensioning and tolerancing per ansi y14.5m-1994. 3. this draw ing conforms to the jedec solid state outline mo-220, variation vhhd except for custom features d2, e2, z, y, and l wh ich are toleranced per supplier designation. 4. r ecommended card reflow profile is per the je dec/ipc j-std-020c specification for small body components.
c8051f326/7 30 rev. 1.1 figure 4.4. qfn-28 recomm ended pcb land pattern table 4.3. qfn-28 pcb land pattern dimensions dimension min max dimension min max c1 4.80 x2 3.20 3.30 c2 4.80 y1 0.85 0.95 e 0.50 y2 3.20 3.30 x1 0.20 0.30 notes: general 1. al l dimensions shown are in millim eters (mm) unless otherwise noted. 2. d imensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. t his land pattern design is based on the ipc-7351 guidelines. solder mask design 4. al l metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 5. a st ainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. the stencil thic kness shoul d be 0.125mm (5 mils). 7. t he ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 8. a 3x3 array of 0.9 0mm openings on a 1.1mm pitch should be used for the center pad to assure the proper paste volume (67% paste coverage). card assembly 9. a no-cl ean, type-3 solder paste is recommended. 10. t he recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
rev. 1.1 31 c8051f326/7 5. voltage regulator (reg0) c8051f326/7 devices include a voltage regulator (reg0). when enabled, the reg0 output appears on the vdd pin and can be used to power external device s. reg0 can be enabled/disabled by software using bit regen in register reg0cn. see ta b l e 5.1 for reg0 electrical characteristics. the voltage regulator is enabled on reset. when the device is self-powered from a 3v supply net, the reg - ulator may be disabled in order to save power. import ant note: if the voltage at the regulator input (regin) is greater than the core supply voltag e (vdd), the voltage regulator should not be dis - abled. otherwise, permanent damage to the device may occur. note that the vbus signal must be connected to th e vbus pin when using the device in a usb network. the vbus signal should only be connected to the re gin pin when operating the device as a bus-powered function. reg0 configuration options are shown in figure 5.1 - figure 5.4 . 5.1. regulator mode selection reg0 offers a low power mode intended for use when the device is in suspend mode. in this low power mode, the reg0 output remains as specified; however the reg0 dynami c performance (response time) is degraded. see ta b l e 5.1 for normal and low power mode supply cu rrent specificati ons. the reg0 mode selection is controlled via the regmod bit in register reg0cn. 5.2. vbus detection when the usb function contro ller is used (see section section ?12. universal serial bus controller (usb0)? on page 87 ), the vbus signal should be connected to the vbus pin. the vbstat bit (register reg0cn) indicates the current logic level of the vbus s ignal. if enabled, a vbus interrupt will be gener - ated when the vbus signal matches the polarity selected by the vbpo l bit in register reg0cn. the vbus interrupt is level-sensitive, and has no asso ciated interrup t pending flag. the vbus interrupt will be active as long as the vbus signal matc hes the polarity selected by vbpol. see ta b l e 5.1 for vbus input parameters. important note: when usb is selected as a reset source , a system reset will be generated when the vbus signal matches the polarity selected by the vbpol bit. see section ?7. reset sources? on page 57 for details on selecting usb as a reset source. table 5.1. voltage regulator electrical specifications v dd = 3.0 v; ?40 to +85 c unless otherwise specified. parameter conditions min typ max units input voltage range 2.7 ? 5.25 v output voltage output current = 1 to 100 ma 3.0 3.3 3.6 v vbus detection input threshold 1.0 1.8 2.9 v bias current normal mode (regmod = ?0?) low power mode (regmod = ?1?) ? ? 75 41 111 61 a dropout voltage (v do )* idd = 1 to 100 ma ? 1 ? mv/ma *note: the minimum input voltage is 2.70 v or v dd + v do (max load), whichever is greater.
c8051f326/7 32 rev. 1.1 figure 5.1. reg0 confi guration: usb bus-powered figure 5.2. reg0 configuration: usb self-powered voltage regulator (reg0) v in v out vbus sense regin vbus from vbus to 3 v power net device power net vdd c8051f326/7 1.0 f 0.1 f 0.1 f 1.0 f voltage regulator (reg0) v in v out vbus sense regin vbus to 3 v power net device power net vdd c8051f326/7 from 5 v power net from vbus 0.1 f 0.1 f 1.0 f 1.0 f
rev. 1.1 33 c8051f326/7 figure 5.3. reg0 conf iguration: usb self-pow ered, regulator disabled figure 5.4. reg0 configur ation: no usb connection voltage regulator (reg0) v in v out vbus sense regin vbus from 3 v power net device power net vdd c8051f326/7 from vbus 0.1 f 1.0 f voltage regulator (reg0) v in v out vbus sense regin vbus to 3 v power net device power net vdd c8051f326/7 from 5 v power net 0.1 f 0.1 f 1.0 f 1.0 f
c8051f326/7 34 rev. 1.1 sfr definition 5.1. reg0cn: voltage regulator control bit7: regdis: voltag e regulator disable. 0: voltage regulator enabled. 1: voltage regulator disabled. bit6: vbstat: vbus signal status. 0: vbus signal currently absent (device not attached to usb network). 1: vbus signal currently present (device attached to usb network). bit5: vbpol: vbus interr upt polarity select. this bit selects the vbus interrupt polarity. 0: vbus interrupt acti ve when vbus is low. 1: vbus interrupt active when vbus is high. bit4: regmod: voltage re gulator mode select. this bit selects the voltage regulator mode. when regmod is set to ?1?, the voltage regu- lator operates in low power (suspend) mode. 0: usb0 voltage regulator in normal mode. 1: usb0 voltage regula tor in low power mode. bits3?0: reserved. read = 0000b. must write = 0000b. r/w r r/w r/w r/w r/w r/w r/w reset value regdis vbstat vbpol regmod reserved res erved reserved reserved 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc9
rev. 1.1 35 c8051f326/7 6. cip-51 microcontroller the mcu system controller core is the cip-51 microcon troller. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemble rs and compilers can be used to develop soft- ware. the mcu family has a superset of all the peripherals included with a standard 8051. included are two 16-bit counter/timers (see description in section ?14. timers? on page 127), an enhanced full-duplex uart (see description in section ?13. uart0? on page 117), 256 bytes of internal ram, 128 byte special function register (sfr) address space (section ?6.2.6. special function registers? on page 43), and 15 port i/o (see description in section ?11. port inpu t/output? on page 79). the cip-51 also includes on-chip debug hardware (see description in section ?15. c2 in terface? on page 135), and interfaces directly with the usb and other digital subsystems providing a complete solution in a single integrated circuit. the cip-51 microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and fu nctions to extend its capability (s ee figure 6.1 for a block diagram). the cip-51 includes the following features: figure 6.1. cip-51 block diagram - fully compatible wit h mcs-51 instruction set - 25 mips peak throughput with 25 mhz clock - 0 to 25 mhz clock frequency - 256 bytes of internal ram -15 port i/o - extended interrupt handler - reset input - power management modes - on-chip debug logic - program and data memory security data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram (256 x 8) d8 stack pointer d8
c8051f326/7 36 rev. 1.1 performance the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan- dard 8051 architecture. in a standar d 8051, all instructions except for mul and div take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 mhz. by contrast, the cip-51 core executes 70% of its instructions in one or tw o system clock cycles, with no instructions taking more than eight system clock cycles. with the cip-51's maximum system clock at 25 mhz, it has a peak throughput of 25 mips. the cip-51 has a total of 109 instructions. the table below shows the total number of instructions that for execution time. programming and debugging support in-system programming of the flash program memory and communication with on-chip debug support logic is accomplished via the silicon laboratories 2-wire development inte rface (c2). note that the re-pro- grammable flash can also be read and changed a single byte at a time by the application software using the movc and movx instructions. this feature allows program memory to be used for non-volatile data storage as well as updating program code under software control. the on-chip debug support logic facilitates full speed in-circuit debugging, a llowing the setting of hardware breakpoints, starting, stopping and single stepping th rough program execution (including interrupt service routines), examination of the program's call stack, a nd reading/writing the conten ts of registers and mem- ory. this method of on-chip debugging is completely non-intrusive, requiring no ram, stack, timers, or other on-chip resources. c2 details can be foun d in section ?15. c2 interface? on page 135. the cip-51 is supported by developm ent tools from silicon la boratories and third pa rty vendors. silicon laboratories provides an integrated development environment (ide) including editor, macro assembler, debugger and programmer. the ide's debugger and programmer interface to the cip-51 via the c2 inter- face to provide fast and efficien t in-system device programming and debugging. third party macro assem- blers and c compilers are also available. 6.1. instruction set the instruction set of the cip-51 system controller is fully compatible with the standard mcs-51? instruc- tion set. standard 8051 development tools can be used to develop software for the cip-51. all cip-51 instructions are the binary and fu nctional equivalent of their mcs-51? counterparts, including opcodes, addressing modes and effect on psw flags. however, in struction timing is different than that of the stan- dard 8051. 6.1.1. instruction and cpu timing in many 8051 implementations, a distinction is ma de between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. however, the cip-51 implementation is based solely on clock cycle timing. all instructio n timings are specified in terms of clock cycles. due to the pipelined architecture of the cip-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. conditional branch instruct ions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken. table 6.1 is the cip-51 instruction set summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. clocks to execute 1 22/333/444/55 8 number of instructions 265051473121
rev. 1.1 37 c8051f326/7 6.1.2. movx instruction and program memory the movx instruction is typically used to access exte rnal data memory (note: the c8051f326/7 does not support off-chip data or program memory). in the cip-51, the movx write instru ction is used to accesses external ram (xram) and the on-chip program memo ry space implemented as re-programmable flash memory. the flash access feature provides a mechanism for the cip-51 to update program code and use the program memory space for non-volatile data storage. refer to section ?8. flash memory? on page 63 for further details. table 6.1. cip-51 instruction set summary mnemonic description bytes clock cycles arithmetic operations add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract indirect ram from a with borrow 1 2 subb a, #data subtract imme diate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a and a to direct byte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 2
c8051f326/7 38 rev. 1.1 orl direct, #data or immediate to direct byte 3 3 xrl a, rn exclusive-or register to a 1 1 xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2 xrl direct, #data exclusive-or immediate to direct byte 3 3 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 2 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 xchd a, @ri exchange low nibble of indirect ram with a 1 2 boolean manipulation clr c clear carry 1 1 table 6.1. cip-51 instructi on set summary (continued) mnemonic description bytes clock cycles
rev. 1.1 39 c8051f326/7 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 anl c, bit and direct bit to carry 2 2 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 jc rel jump if carry is set 2 2/3 jnc rel jump if carry is not set 2 2/3 jb bit, rel jump if direct bit is set 3 3/4 jnb bit, rel jump if direct bit is not set 3 3/4 jbc bit, rel jump if direct bit is set and clear bit 3 3/4 program branching acall addr11 absolute subroutine call 2 3 lcall addr16 long subroutine call 3 4 ret return from subroutine 1 5 reti return from interrupt 1 5 ajmp addr11 absolute jump 2 3 ljmp addr16 long jump 3 4 sjmp rel short jump (relative address) 2 3 jmp @a+dptr jump indirect relative to dptr 1 3 jz rel jump if a equals zero 2 2/3 jnz rel jump if a does not equal zero 2 2/3 cjne a, direct, rel compare direct byte to a and jump if not equal 3 3/4 cjne a, #data, rel compare immediate to a and jump if not equal 3 3/4 cjne rn, #data, rel compare immediate to register and jump if not equal 33/4 cjne @ri, #data, rel compare immediate to indirect and jump if not equal 34/5 djnz rn, rel decrement regist er and jump if not zero 2 2/3 djnz direct, rel decrement direct byte and jump if not zero 3 3/4 nop no operation 1 1 table 6.1. cip-51 instructi on set summary (continued) mnemonic description bytes clock cycles
c8051f326/7 40 rev. 1.1 notes on registers, operands and addressing modes: rn - register r0-r7 of the currently selected register bank. @ri - data ram location address ed indirectly through r0 or r1. rel - 8-bit, signed (2s complement) offset relative to t he first byte of the followi ng instruction. used by sjmp and all conditional jumps. direct - 8-bit internal data location?s address. this could be a direct-access data ram location (0x00- 0x7f) or an sfr (0x80-0xff). #data - 8-bit constant #data16 - 16-bit constant bit - direct-accessed bit in data ram or sfr addr11 - 11-bit destination address used by acall and ajmp. the destination mu st be within the same 2 kb page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by lcall a nd ljmp. the destination may be anywhere within the 8 kb program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980.
rev. 1.1 41 c8051f326/7 6.2. memory organization the memory organization of the cip-51 system controller is similar to that of a standard 8051. there are two separate memory spaces: program memory and data memory. program and data memory share the same address space but are accessed via different in struction types. the cip-51 memory organization is shown in figure 6.2. figure 6.2. memory map 6.2.1. program memory the cip-51 core has a 64 kb program memory space. the c8051f326/7 implements 16k kb of this pro- gram memory space as in-system, re-programmable flash memory, organized in a contiguous block from addresses 0x0000 to 0x3fff. addresses above 0x3dff are reserved. program memory is normally assumed to be read-only . however, the cip-51 can write to program memory by setting the program store write enable bit (psctl.0) and using the movx instru ction. this feature pro- vides a mechanism for the cip-51 to update program code and use the program memory space for non- volatile data storage. refer to section ?8. flash memory? on page 63 for further details. same 1024 bytes as from 0x0000 to 0x03ff, wrapped on 1k-byte boundaries program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 1024 bytes (accessable using movx instruction) 0x0000 0x03ff 0x0400 0xffff 16k flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0x3e00 0x3dff usb fifos 256 bytes accessible through usb registers only 0x3fff
c8051f326/7 42 rev. 1.1 6.2.2. data memory the cip-51 includes 256 of internal ram mapped in to the data memory space from 0x00 through 0xff. the lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. either direct or indirect addressing may be used to access the lower 128 bytes of data memory. locations 0x00 through 0x1f are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. the next 16 bytes, location s 0x20 through 0x2f, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. the upper 128 bytes of data memory are accessible only by indirect addressing. this region occupies the same address space as the special function regist ers (sfr) but is physically separate from the sfr space. the addressing mode used by an instruction when accessing locations above 0x7f determines whether the cpu accesses the upper 128 bytes of data memory space or the sfrs. instructions that use direct addressing will access the sfr space. instructions using indirect addressing above 0x7f access the upper 128 bytes of data memory. figure 6.2 illustrates the data memory organization of the cip-51. 6.2.3. general purpose registers the lower 32 bytes of data memory, locations 0x00 through 0x1f, may be addressed as four banks of gen- eral-purpose registers. each bank consists of eigh t byte-wide registers designated r0 through r7. only one of these banks may be enabled at a time. two bi ts in the program status word, rs0 (psw.3) and rs1 (psw.4), select the active register bank (see description of the psw in figure 6.4). this allows fast context switching when entering subroutines and interrupt serv ice routines. indirect addressing modes use regis- ters r0 and r1 as index registers. 6.2.4. bit addressable locations in addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from 0x00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0x07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distinguished from a full byte access by the type of instruction used (bit source or destinat ion operands as opposed to a byte source or destina- tion). the mcs-51? assembly language allows an alternate notation for bit addressing of the form xx.b where xx is the byte address and b is the bit position within the byte. for example, the instruction: mov c, 22h.3 moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag. 6.2.5. stack a programmer's stack can be located anywhere in the 256-byte data memory. the stack area is desig- nated using the stack pointer (sp, 0x81) sfr. the sp will poin t to the last location used. the next value pushed on the stack is placed at sp +1 and then sp is incremented. a re set initializes the stack pointer to location 0x07. therefore, the first value pushed on the st ack is placed at location 0x08, which is also the first register (r0) of register bank 1. thus, if more than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes.
rev. 1.1 43 c8051f326/7 6.2.6. special function registers the direct-access data memory locations from 0x80 to 0xff constitute the sp ecial function registers (sfrs). the sfrs provide control and data exchang e with the cip-51's resources and peripherals. the cip-51 duplicates the sfrs found in a typical 805 1 implementation as well as implementing additional sfrs used to configure and access the sub-systems uni que to the mcu. this allows the addition of new functionality while retaining compatibility with the mcs-51? instruction set. table 6.2 lists the sfrs imple- mented in the cip-51 system controller. the sfr registers are accessed anytime the direct ad dressing mode is used to access memory locations from 0x80 to 0xff. sfrs with addresses ending in 0x0 or 0x8 (e.g., p0, tcon, scon0, ie, etc.) are bit- addressable as well as byte-addressable. all other sfrs are byte-addressable only. unoccupied addresses in the sfr space are reserved for future use. accessing t hese areas will have an indeterminate effect and should be avoided. refer to the corres ponding pages of the data sheet, as indicated in table 6.3, for a detailed description of each register. table 6.2. special function regist er (sfr ) memory map f8 vdm0cn f0 b eip1 eip2 e8 rstsrc e0 acc gpiocn osclcn eie1 eie2 d8 d0 psw usb0xcn c8 reg0cn c0 b8 ip clkmul b0 p3 oscicn oscicl flscl flkey a8 ie clksel emi0cn a0 p2 p0mdout p2mdout p3mdout 98 scon0 sbuf0 smod0 90 sbcon0 sbrll0 sbrlh0 usb0adr usb0dat 88 tcon tmod tl0 tl1 th0 th1 ckcon psctl 80 p0 sp dpl dph pcon 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) (bit addressable) table 6.3. special function registers sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address description page acc 0xe0 accumulator 46 b 0x f0 b register 47 ckcon 0x8e clock control 133 clkmul 0x91 clock multiplier 75 clksel 0xa9 clock select 77 dph 0x83 data pointer high 45 dpl 0x82 data pointer low 45 eie1 0xe6 extended interrupt enable 1 53
c8051f326/7 44 rev. 1.1 eie2 0xe7 extended interrupt enable 2 53 eip1 0x f6 extended interrupt priority 1 53 eip2 0x f7 extended interrupt priority 2 54 emi0cn 0x aa external memory interface control 70 flkey 0xb7 flash lock and key 67 flscl 0xb6 flash scale 67 gpiocn 0xe2 global port i/o control 82 ie 0xa8 interrupt enable 51 ip 0xb8 interrupt priority 52 oscicl 0xb3 internal oscillator calibration 73 oscicn 0xb2 internal oscillator control 72 osclcn 0xe3 low frequency internal os cillator control 74 p0 0x80 port 0 latch 82 p0mdout 0xa4 port 0 output mode configuration 82 p2 0xa0 port 2 latch 83 p2mdout 0xa6 port 2 output mode configuration 83 p3 0xb0 port 3 latch 83 p3mdout 0xa7 port 3 output mode configuration 84 pcon 0x87 power control 56 psctl 0x 8f program store r/w control 66 psw 0xd0 program status word 46 rstsrc 0xef reset source configuration/status 61 sbuf0 0x99 uart0 data buffer 125 sbcon0 0x91 baudrate generator 0 control 125 sbrlh0 0x94 baudrate generator 0 reload value high byte 126 sbrll0 0x93 baudrate generator 0 reload value low byte 126 scon0 0x98 uart0 control 123 smod0 0x9a uart0 mode 124 sp 0x81 stack pointer 45 tcon 0x88 timer/counter control 131 th0 0x8c timer/counter 0 high 134 th1 0x8d timer/counter 1 high 134 tl0 0x8a timer/counter 0 low 134 tl1 0x8b timer/counter 1 low 134 tmod 0x89 timer/counter mode 132 usb0adr 0x96 indirect address register 91 usb0dat 0x97 data register 92 usb0xcn 0xd7 transceiver control 89 vdm0cn 0xff vdd monitor control 59 table 6.3. special functi on registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address description page
rev. 1.1 45 c8051f326/7 6.2.7. register descriptions following are descriptions of sfrs related to the operati on of the cip-51 system controller. reserved bits should not be set to logic l. future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default state. detailed descriptions of the remaining sfrs are included in the sections of t he data sheet associated with their corresponding sys- tem function. sfr definition 6.1. dpl: data pointer low byte sfr definition 6.2. dph: data pointer high byte sfr definition 6.3. sp: stack pointer bits7?0: dpl: data pointer low. the dpl register is the low byte of the 16-b it dptr. dptr is used to access indirectly addressed memory. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x82 bits7?0: dph: data pointer high. the dph register is the high byte of the 16-b it dptr. dptr is used to access indirectly addressed memory. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x83 bits7?0: sp: stack pointer. the stack pointer holds the location of the top of the stack. the stack pointer is incremented before every push operation. the sp r egister defaults to 0x07 after reset. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x81
c8051f326/7 46 rev. 1.1 sfr definition 6.4. psw: program status word sfr definition 6.5. acc: accumulator bit7: cy: carry flag. this bit is set when the last arithmetic operat ion resulted in a carry (addition) or a borrow (subtraction). it is cleared to logi c 0 by all other arithmetic operations. bit6: ac: auxiliary carry flag this bit is set when the last arithmetic operati on resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to logic 0 by all other arithmetic opera- tions. bit5: f0: user flag 0. this is a bit-addressable, general purpose flag for use under software control. bits4?3: rs1-rs0: register bank select. these bits select which register ban k is used during register accesses. bit2: ov: overflow flag. this bit is set to 1 under the following circumstances: ? an add, addc, or subb instructi on causes a sign-change overflow. ? a mul instruction results in an overflow (result is greater than 255). ? a div instruction causes a divide-by-zero condition. the ov bit is cleared to 0 by the add, addc, subb, mul, and div inst ructions in all other cases. bit1: f1: user flag 1. this is a bit-addressable, general purpose flag for use under software control. bit0: parity: parity flag. r/w r/w r/w r/w r/w r/w r/w r reset value cy ac f0 rs1 rs0 ov f1 parity 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xd0 rs1 rs0 register bank address 0 0 0 0x00?0x07 0 1 1 0x08?0x0f 1 0 2 0x10?0x17 1 1 3 0x18?0x1f bits7?0: acc: accumulator. this register is the accumulator for arithmetic operations. r/w r/w r/w r/w r/w r/w r/w r/w reset value acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xe0
rev. 1.1 47 c8051f326/7 sfr definition 6.6. b: b register bits7?0: b: b register. this register serves as a second accumu lator for certain arithmetic operations. r/w r/w r/w r/w r/w r/w r/w r/w reset value b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xf0
c8051f326/7 48 rev. 1.1 6.3. interrupt handler the cip-51 includes an extended interrupt system support ing a total of 8 interrupt sources with two priority levels. the allocation of interrupt sources between on -chip peripherals and external inputs pins varies according to the specific version of the device. each interrupt source, with the exception of usb0, has one or more associated interrupt-pending flag(s) located in an sfr. usb0 in terrupt sources are located in the usb registers. see section ?12.8. interrupts? on page 101 for more details about the usb interrupt. when a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. if interrupts are enabled for the source, an interrupt req uest is generated when the interrupt-pending flag is set. as soon as execution of the current instructio n is complete, the cpu generates an lcall to a prede- termined address to begin execution of an interrupt se rvice routine (isr). each isr must end with an reti instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (the interrupt-pending flag is set to logic 1 regard- less of the interrupt's enable/disable state.) each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an sfr (ie-eie2). ho wever, interrupts must first be globally enabled by setting the ea bit (ie.7) to logic 1 before the individual interrupt enabl es are recognized. setting the ea bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. note: any instruction which clears the ea bit should be immediately followed by an instruction which has two or more opcode bytes. for example: // in 'c': ea = 0; // clear ea bit ea = 0; // ... followed by another 2-byte opcode ; in assembly: clr ea ; clear ea bit clr ea ; ... followed by another 2-byte opcode if an interrupt is posted during the execution phase of a "clr ea" opcode (or any instruction that clears the ea bit), and the instruction is followed by a single-cycle instruction, the interrupt ma y be taken. if the ea bit is read inside the interrupt service routine, it will return a '0'. when the "clr ea" opcode is followed by a multi-cycle instruction, th e interrupt will not be taken. some interrupt-pending flags are automatically cleare d by the hardware when the cpu vectors to the isr. however, most are not cleared by the hardware and must be cleared by software before returning from the isr. if an interrupt-pending flag remains set after the cpu completes the return-from-interrupt (reti) instruction, a new interr upt request will be gen erated immediately and the cpu will re-enter the isr after the completion of th e next instruction. 6.3.1. mcu interrupt sources and vectors the mcu supports 8 interrupt sources. software can simulate an interrupt by setting any interrupt-pending flag to logic 1. if interr upts are enabled for the flag, an interrupt request will be generated and the cpu will vector to the isr address associated with the interr upt-pending flag. mcu interrupt sources, associated vector addresses, priority order and control bits ar e summarized in table 6.5 on page 50. refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt condi- tions for the peripheral and the behavior of its interrupt-pending flag(s).
rev. 1.1 49 c8051f326/7 6.3.2. external interrupts the /int0 external interrupt source can be configured as edge or level sensitive. the it0 bit (tcon.0, see figure 14.1 on page 128) selects level or edge sensitivity. when global port i/o inputs are enabled, /int0 will monitor the voltage at the input pin. the cpu will vect or to the /int0 interrupt service routine whenever the pin detects the condition the external interrupt has been configured to monitor. tmod.3 (gate0) con- trols the functionality of /int0 as is shown in table 6.4. the /int1 interrupt source provides an interrupt on two events, based on the logic level of gate1 (tmod.7). if gate1 is set to logic 1, an interrupt is generated every two low fr equency internal oscillator clock cycles. this allows the cpu to vector to the /int 1 interrupt service routine at a rate of 40 khz. if gate1 is set to logic 0, an interr upt is generated when the internal oscillator re sumes from a suspended state. the pending flags for the /int0 and /int1 interrupts are set upon reset. if the /int0 or /int1 interrupt is used, the respective flag should be cleared before e nabling the interrupts to prevent an accidental inter- rupt. the pending flags are for the /int0 and /int1 interrupt are in the tcon register. 6.3.3. interrupt priorities each interrupt source can be individually programmed to one of two priority levels: low or high. a low prior- ity interrupt service routine can be pree mpted by a high priority interrupt. a high priority interrupt cannot be preempted. each interrupt has an associated interrupt priority bit in an sfr (ip or eip2) used to configure its priority level. low priority is th e default. if two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. if both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in table 6.5. 6.3.4. interrupt latency interrupt response time depends on the state of the cpu when the interrupt occurs. pending interrupts are sampled and priority decoded each sys tem clock cycle. therefore, the fa stest possible response time is 5 system clock cycles: 1 clock cycle to detect the interr upt and 4 clock cycles to complete the lcall to the isr. if an interrupt is pending when a reti is execut ed, a single instruction is executed before an lcall is made to service the pending interrupt. therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new in terrupt is of greater priority) occurs when the cpu is performing an reti instruct ion followed by a div as the next instructio n. in this case, th e response time is 18 system clock cycles: 1 clock cycle to detect the in terrupt, 5 clock cycles to execute the reti, 8 clock cycles to complete the div instruction and 4 clock cycl es to execute the lcall to the isr. if the cpu is executing an isr for an interr upt with equal or higher pr iority, the new interrupt will not be serviced until the current isr completes, including the reti and following instruction. the cpu is stalled during flash writ e/erase operations. interr upt service latency will be increased for inter- rupts occurring while the cpu is stalled. the latency for these situations will be determined by the standard interrupt service procedure (as described above ) and the amount of time the cpu is stalled. table 6.4. tmod.3 control of /int0 tmod.3 = 0 tmod.3 = 1 /int0 pinout p0.0 p0.2 edge sensitivity rising edge falling edge level sensitivity active high active low
c8051f326/7 50 rev. 1.1 6.3.5. interrupt register descriptions the sfrs used to enable the interrupt sources and set t heir priority level are described below. refer to the data sheet section associated with a particular on-chi p peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). table 6.5. interrupt summary interrupt source interrupt vector priority order pending flag bit addressable? cleared by hw? enable flag priority control reset 0x0000 to p none n/a n/a always enabled always highe st external interrupt 0 (/ int0) 0x0003 0 ie0 (tcon.1) y y ex0 (ie.0) px0 (ip .0) timer 0 overflow 0x000b 1 tf0 (tcon.5) y y et0 (ie.1) pt0 (ip.1) external interrupt 1 (/ int1) 0x0013 2 ie1 (tcon.3) y y ex1 (ie.2) px1 (ip .2) timer 1 overflow 0x001b 3 tf1 (tcon.7) y y et1 (ie.3) pt1 (ip.3) uart0 0x0023 4 ri0 (scon0.0) ti0 (scon0.1) y n es0 (ie.4) ps0 (ip .4) usb0 0x0043 8 special* n n eusb0 (eie1.1) pusb0 (eip1.1) vbus level 0x007b 15 n/a n/a n/a evbus (eie2.0) pvbus (eip2.0) *note: see section ?12.8. interrupts? on page 101 for more details abo ut the usb interrupt.
rev. 1.1 51 c8051f326/7 sfr definition 6.7. ie: interrupt enable bit7: ea: enable all interrupts. this bit globally enables/disabl es all interrupts. it overrides the individual interrupt mask set- tings. 0: disable all interrupt sources. 1: enable each interrupt accord ing to its individual mask setting. bit6?5: unused. read = 00b. write = don?t care. bit4: es0: enable uart0 interrupt. this bit sets the masking of the uart0 interrupt. 0: disable uart0 interrupt. 1: enable ua rt0 interrupt. bit3: et1: enable timer 1 interrupt. this bit sets the masking of the timer 1 interrupt. 0: disable all ti mer 1 interrupt. 1: enable interrupt requests generated by the tf1 flag. bit2: ex1: enable exte rnal interrupt 1. this bit sets the masking of external interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the /int1 input. bit1: et0: enable timer 0 interrupt. this bit sets the masking of the timer 0 interrupt. 0: disable all ti mer 0 interrupt. 1: enable interrupt requests generated by the tf0 flag. bit0: ex0: enable exte rnal interrupt 0. this bit sets the masking of external interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the /int0 input. r/w r r r/w r/w r/w r/w r/w reset value ea ? ? es0 et1 ex1 et0 ex0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xa8
c8051f326/7 52 rev. 1.1 sfr definition 6.8. ip: interrupt priority bit7?5: unused. read = 100b. write = don't care. bit4: ps0: uart0 interrupt priority control. this bit sets the priority of the uart0 interrupt. 0: uart0 interrupt set to low priority level. 1: uart0 interrupts set to high priority level. bit3: pt1: timer 1 interr upt priority control. this bit sets the priority of the timer 1 interrupt. 0: timer 1 interrupt set to low priority level. 1: timer 1 interrupts set to high priority level. bit2: px1: external interr upt 1 priority control. this bit sets the priority of the ex ternal interrupt 1 interrupt. 0: external interrupt 1 set to low priority level. 1: external interrupt 1 set to high priority level. bit1: pt0: timer 0 interr upt priority control. this bit sets the priority of the timer 0 interrupt. 0: timer 0 interrupt set to low priority level. 1: timer 0 interrupt set to high priority level. bit0: px0: external interr upt 0 priority control. this bit sets the priority of the ex ternal interrupt 0 interrupt. 0: external interrupt 0 set to low priority level. 1: external interrupt 0 set to high priority level. r r r r/w r/w r/w r/w r/w reset value ? ? ? ps0 pt1 px1 pt0 px0 10000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xb8
rev. 1.1 53 c8051f326/7 sfr definition 6.9. eie1: extended interrupt enable 1 sfr definition 6.10. eip1: extended interrupt priority 1 sfr definition 6.11. eie2: extended interrupt enable 2 bit7?2: unused. read = 000000b. write = don?t care. bit1: eusb0: enable usb0 interrupt. this bit sets the masking of the usb0 interrupt. 0: disable all u sb0 interrupts. 1: enable interrupt requests generated by usb0. bit0: unused. read = 0. write = don?t care. r r r r r r r/w r reset value ??????eusb0?00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe6 bit7?2: unused. read = 000000b. write = don?t care. bit1: pusb0: usb0 interr upt priority control. this bit sets the priority of the usb0 interrupt. 0: usb0 interrupt set to low priority level. 1: usb0 interrupt set to high priority level. bit0: unused. read = 0. write = don?t care. r r r r r r r/w r reset value ? ? ? ? ? ? pusb0 ? 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf6 bits7?1: unused. read = 0000000b. write = don?t care. bit0: evbus: enable vbus level interrupt. this bit sets the masking of the vbus interrupt. 0: disable all vbus interrupts. 1: enable interrupt requests generated by vbus level sense. r r r r r r r r/w reset value ? ? ? ? ? ? ? evbus 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe7
c8051f326/7 54 rev. 1.1 sfr definition 6.12. eip2: extended interrupt priority 2 bits7?1: unused. read = 0000000b. write = don?t care. bit0: pvbus: vbus level inte rrupt priority control. this bit sets the priority of the vbus interrupt. 0: vbus interrupt set to low priority level. 1: vbus interrupt set to high priority level. r r r r r r r r/w reset value ? ? ? ? ? ? ? pvbus 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf7
rev. 1.1 55 c8051f326/7 6.4. power management modes the cip-51 core has two software programmable power management modes: idle and stop. idle mode halts the cpu while leaving the peripherals and clocks active. in stop mode, the cpu is halted, all inter- rupts, are inactive, and the internal oscillator is stopped (the voltage regulator, lo w frequency os cillator, and external clock remain in their selected state). since clocks are running in idle mode, power consumption is dependent upon t he system clock frequency and t he number of peripherals left in active mode before entering idle. stop mode consumes the least power. figure 6.13 describes the power control register (pcon) used to control the cip-51's power management modes. although the cip-51 has idle and stop modes built in (as with any standard 8051 architecture), power management of the entire mcu is better accomplished through system clock and individual peripheral management. digital peripherals, such as timers or uart , draw little power when they are not in use. turn- ing off the oscillators lowers power consumption considerably; however a reset is required to restart the mcu. the internal oscillator can be placed in suspend mode (see section ?1 0. oscillators? on page 71). in sus- pend mode, the intern al oscillator is stopped until a non-idle u sb event is detected, or the vbus input sig- nal matches the polarity selected by the vbpol bit in register re g0cn (figure 5.1 on page 34). 6.4.1. idle mode setting the idle mode select bit (pcon.0) causes the cip-51 to halt the cpu and enter idle mode as soon as the instruction that sets the bit completes executio n. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt is asserted or a reset occurs. the assertion of an enabled interrupt will cause the idle mode selection bit (pcon.0) to be cleared and the cpu to resume operation. the pen ding interrupt will be serviced and the next in struction to be executed after the return from interrupt (reti) will be the instruction immedi ately following the one that se t the idle mode select bit. if idle mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. 6.4.2. stop mode setting the stop mode select bit (pcon.1) causes the ci p-51 to enter stop mode as soon as the instruc- tion that sets the bit comp letes execution. in stop mo de the internal oscillator, cpu, and all digital peripher- als are stopped; the state of the low frequency oscillato r is not affected. each an alog peripheral (including the low frequency oscilla tor) may be shut dow n individually prior to entering stop mode. stop mode can only be terminated by an internal or external reset. on reset, the cip-51 performs the normal reset sequence and begins program execution at address 0x0000. if enabled, the missing clock detect or will cause an internal reset and ther eby terminate th e stop mode. the missing clock detector should be disabled if the cpu is to be put to in stop mode for longer than the mcd timeout of 100 s.
c8051f326/7 56 rev. 1.1 sfr definition 6.13. pcon: power control bits7?2: gf5-gf0: general purpose flags 5-0. these are general purpose flags for use under software control. bit1: stop: stop mode select. setting this bit will place the cip-51 in stop mode. this bit will always be read as 0. 1: cpu goes into stop mode (internal oscillator stopped). bit0: idle: idle mode select. setting this bit will place the cip-51 in idle mode. this bit will always be read as 0. 1: cpu goes into idle mode. (shuts off clock to cpu, but clock to time rs, interrupts, serial ports, and usb0 are still active.) r/w r/w r/w r/w r/w r/w r/w r/w reset value gf5 gf4 gf3 gf2 gf1 gf0 stop idle 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x87
rev. 1.1 57 c8051f326/7 7. reset sources reset circuitry allows the controller to be easily placed in a predefined default condition. on entry to this reset state, th e following occur: ? cip-51 halts program execution ? special function registers (sfrs) are initialized to their defined reset values ? external port pins are forced to a known state ? interrupts and timers are disabled. all sfrs are reset to the predefined values noted in the sfr detailed descriptions. the contents of internal d ata memory are unaffected during a reset; any prev iously stored data is preserved. however, since the stack pointer sfr is reset, the stack is effectively lo st even though the data on the stack is not altered. the port i/o latches are reset to 0xff (all logic ones) in open-drain mode. weak pullups are enabled dur - ing and after the reset. for vdd monitor and power-on resets, the rst pin is driven low until the device exits the reset state. on exit from the reset state, the program counter (pc) is reset, and the system clock defaults to the inter - nal oscillator. refer to section ?10. oscillators? on page 71 for information on selecting and configuring the system clock source. program execut io n begins at location 0x0000. figure 7.1. reset sources missing clock detector (one- shot) (software reset) system reset reset funnel en swrsf internal oscillator system clock cip-51 microcontroller core extended interrupt handler clock select mcd enable xtal2 external clock input errant flash operation /rst (wired-or) power on reset + - vdd supply monitor enable '0' low frequency oscillator
c8051f326/7 58 rev. 1.1 7.1. power-on reset during power-up, the device is held in a reset state and the rst pin is driven low until vdd settles above v rst . a power-on reset delay (t pordelay ) occurs before the device is released from reset; this delay is typically less than 0.3 ms. figure 7.2 . plots the power-on and vdd monitor reset timing. on exit from a power-on reset, the porsf flag (rstsrc.1) is set by hardware to logic 1. when porsf is set, all of the other reset flags in the rstsrc regist er are indeterminate (porsf is cleared by all other resets). since all resets cause program execution to begin at the same location (0x0000) software can read the porsf flag to determine if a power-up was t he cause of reset. the content of internal data mem - ory should be assumed to be undefined after a power-on reset. the vdd monitor is enabled following a po wer-on reset. software can force a power-on reset by writin g ?1? to the pinrsf bit in register rstsrc. figure 7.2. power-on and vdd monitor reset timing power-on reset vdd monitor reset /rst t volts 1.0 2.0 logic high logic low t pordelay v d d 2.70 2.4 v rst vdd
rev. 1.1 59 c8051f326/7 7.2. power-fail r eset / vdd monitor when a power-down transition or power irregularity causes vdd to drop below v rst , the power supply monitor will drive the rst pin low and hold the cip-51 in a reset state (see figure 7.2 ). when vdd returns to a level above v rst , the cip-51 will be released from the reset state. note that even though internal data memory contents are not altered by the power-fail re set, it is impossible to determine if vdd dropped below the level required for data retention. if the porsf flag reads ?1?, the data may no longer be valid. the vdd monitor is enabled after power-on resets; however its defined state (enabled/disabled) is not altered by any other reset source. for example, if th e vdd monitor is enabled and a software reset is per - formed, the vdd monitor will still be enabled af ter the reset. important note: the vdd monitor must be enabled before it is selected as a reset source. selecting the vdd monitor as a reset source before it is enabled and stabilized will cause a system reset. the procedure for configuring the vdd monitor as a reset source is shown below: step 1. enable the vdd monitor (vdm0cn.7 = ?1?). s tep 2. wait for the vdd monitor to stabilize (see table 7.1 for the vdd monitor turn-on time). step 3. select the vdd monitor as a reset source (rstsrc.1 = ?1?). see figure 7.2 for vdd monitor timing. see ta b l e 7.1 for complete electrical characterist ics of the vdd monitor. sfr definition 7.1. vdm0cn: vdd monitor control bit7: vdmen: vdd monitor enable. this bit turns the vdd monitor circuit on/of f. the vdd monitor cannot generate system resets until it is also select ed as a reset source in register rstsrc (figure 7.2). the vdd monitor must be allowed to stabilize before it is selected as a reset source. selecting the vdd monitor as a reset source before it has stabilized may generate a system reset. see table 7.1 for the minimum vdd monitor tu rn-on time. the vdd mo nitor is enabled fol- lowing all por resets. 0: vdd monitor disabled. 1: vdd monitor enabled. bit6: vddstat: vdd status. this bit indicates the current power supply status (vdd monitor output). 0: vdd is at or below the vdd monitor threshold. 1: vdd is above the vdd monitor threshold. bits5?0: reserved. read = variable. write = don?t care. r / wrrrrrrrr e s e t v a l u e vdmen vddstat reserved reserved reserved reserved reserved reserved variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xff
c8051f326/7 60 rev. 1.1 7.3. external reset the external rst pin provides a means for external circuitry to force the device into a reset state. assert - ing an active-low signal on the rst pin generates a reset; an external pullup and/or decoupling of the rst pin may be necessary to avoid erroneous noise-induced resets. see ta b l e 7.1 for complete rst pin spec - ifications. the pinrsf flag (rstsrc.0) is se t on exit from an external reset. 7.4. missing clock detector reset the missing clock detector (mcd) is a on e-shot circuit that is triggered by the system clock. if more than 100 s pass between rising edges on the system clock, the one-shot will time ou t and generat e a reset. after a mcd reset, the mcdrsf flag (rstsrc.2) will read ?1?, signifying the mcd as the reset source; otherwise, this bit reads ?0?. writ ing a ?1? to the mcdrsf bit enables the missing clock detector; writing a ?0? disables it. the state of the rst pin is unaffected by this reset. 7.5. flash error reset if a flash read/write/era se or program read targets an illegal address, a system reset is generated. this may occur due to any of the following: ? a flash write or erase is attempted above user code space. this occurs when pswe is set to ?1? and a movx write operation is attempted above address 0x3dff. ? a flash read is attempted above user code space. th is occurs when a movc operation is attempted above address 0x3dff. ? a program read is attempted above user code spac e. this occu rs when user code attempts to branch to an address above 0x3dff. ? a flash read, write or erase attempt is re stricted d ue to a flash security setting (see section ?8.3. security options? on page 65). the ferror bit (rstsrc.6) is set following a flash error reset. the state of the rst pin is unaffected by this reset. 7.6. software reset software may force a reset by writing a ?1? to the swrsf bit (rstsrc.4). the swrsf bit will read ?1? fol - lowing a software forced reset. the state of the rst pin is unaffected by this reset. 7.7. usb reset writing ?1? to the usbrsf bit in register rstsrc sele cts usb0 as a reset source . with usb0 selected as a reset source, a system reset will be generated when either of the following occur: 1. reset signaling is detected on the usb network. the usb func tion controller (usb0) must be enabled for reset signa ling to be detected. see section ?12. universal serial bus con - troller (usb0)? on page 87 for information on the usb function controller. 2. the voltage on the vbus pin matches the po larity selected by the vbpol bit in register reg0cn. see section ?5. voltage regulator (reg0)? on page 31 for details on the vbus detection circuit. the usbrsf bit will read ?1? followin g a usb reset. the state of the rst pin is unaffected by this reset.
rev. 1.1 61 c8051f326/7 sfr definition 7.2. rstsrc: reset source bit7: usbrsf: usb reset flag 0: read: last reset was not a usb reset; write: usb resets disabled. 1: read: last reset was a usb reset; write: usb resets enabled. bit6: ferror: flash error indicator. 0: source of last reset was not a flash read/write/erase error. 1: source of last reset was a flash read/write/erase error. bit5: unused. read = 0. write = don?t care. bit4: swrsf: software reset force and flag. 0: read: source of last reset was not a write to the swrsf bit; write: no effect. 1: read: source of last was a write to the swrsf bit; write: forces a system reset. bit3: unused. read = 0. write = don?t care. bit2: mcdrsf: missing clock detector flag. 0: read: source of last reset was not a missing clock detector timeout; write: missing clock detector disabled. 1: read: source of last reset was a missing clock detector timeout; write: missing clock detector enabled; triggers a reset if a missing clock condition is detected. bit1: porsf: power-on / vdd monitor reset flag. this bit is set anytime a power-on reset occu rs. writing this bit selects/deselects the vdd monitor as a reset source. note: writing ?1? to this bit before the vdd monitor is enabled and stabilized can cause a system reset. see register vdm0cn (figure 7.1). 0: read: last reset was not a power-on or vdd monitor reset; write: vdd monitor is not a reset source. 1: read: last reset was a power-on or vdd monitor reset; all other reset flags indetermi- nate; write: vdd monitor is a reset source. bit0: pinrsf: hw pin reset flag. 0: source of last reset was not rst pin. 1: source of la st reset was rst pin. note: do not use read-modify-write instructions on this register. r/w r r r/w r r/w r/w r reset value usbrsf ferror ? swrsf ? mcdrsf porsf pinrsf variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xef
c8051f326/7 62 rev. 1.1 table 7.1. reset electrical characteristics ?40 to +85 c unless otherwise specified. parameter conditions min typ max units ?f326 rst output voltage i ol = ?8.5 ma; vio = 2.7 to 3.6 v i ol = ?8.5 ma; vio = 2.0 v; ? ? 0.6 0.6 v ?f327 rst output voltage i ol = ?8.5 ma; vio = 2.7 to 3.6 v ? ? 0.6 v rst input high voltage* 0.7 x vio ? ? v rst input low voltage* ? ? 0.3 x vio v ?f326 rst pullup current 10 26 40 a ?f327 rst pullup current ? 26 40 a vdd monitor threshold (v rst ) 2.40 2.55 2.70 v missing clock detector timeout time from last system clock rising edge to reset initiation 100 240 500 s reset time delay delay between the release of any re set source and code execution at location 0x0000 5.0 ? ? s minimum rst low time to generate a system reset 15 ? ? s vdd monitor turn-on time 100 ? ? s vdd monitor supply current ? 20 50 a *note: on 'f327 devices, vio = vdd.
rev. 1.1 63 c8051f326/7 8. flash memory on-chip, re-programmable flash memory is included fo r program code and non-volatile data storage. the flash memory can be programmed in-system, a single by te at a time, through the c2 interface or by soft - ware using the movx instruction. once cleared to logic 0, a f lash bit must be erased to set it back to logic 1. flash bytes would typically be erased (set to 0xff) before being reprogrammed. the write and erase operations are automatically timed by hardware for pr oper execution; data pollin g to determine the end of the write/erase operation is not required. code execut ion is stalled during a flash write/erase operation. refer to ta b l e 8.1 for complete flash memory electrical characteristics. 8.1. programming the flash memory the simplest means of programming the flash memory is through the c2 interface using programming tools provided by silicon laboratories or a th ird party vendor. this is the only means for programming a non-initialized device. for details on the c2 commands to program flash memory, see section ?15. c2 interface? on page 135 . to ensure the integrity of flash contents, it is strongly recommended that the on-chip vdd monitor be enabled in any system that includes code that writes and/or erases flash memory from soft - ware. 8.1.1. flash lock and key functions flash writes and erases by user so ftware are protected with a lock and key function. the flash lock and key register (flkey) must be writ ten with the correct key codes, in sequence, be fore flash operations may be performed. the key codes are: 0xa5, 0xf1. the timing does not matter, but the codes must be written in order. if the key codes are written out of or der, or the wrong codes are written, flash writes and erases will be disabled until the next system reset. flash writes and eras es will also be disabled if a flash write or erase is attempted before the key codes have been written properly. the flash lock resets after each write or erase; the key codes must be writte n again before a following flash operation can be per - formed. the flkey regist er is det ailed in figure 8.2 . 8.1.2. flash erase procedure the flash memory can be programmed by software using the movx write instru ction with the address and data byte to be programmed provided as normal ope rands. before writing to flash memory using movx, flash write operations must be enabled by: (1) writi ng the flash key codes in sequence to the flash lock register (flkey); and (2) setting the pswe program st ore write enable bit (psc tl.0) to logic 1 (this directs the movx writes to target flash memory). the pswe bit remains set until cleared by software. a write to flash memory can clear bits to logic 0 but cann ot set them; only an erase operation can set bits to logic 1 in flash. a byte location to be programmed must be erased before a new value is written. the flash memory is organized in 512-byte pages. the erase operation applies to an entire page (setting all bytes in the page to 0xff). to erase an en tire 512-byte page, perform the following steps: step 1. disable interrupts (recommended). s tep 2. write the first key code to flkey: 0xa5. step 3. write the second key code to flkey: 0xf1. step 4. set the psee bit (register psctl). step 5. set the pswe bit (register psctl). step 6. using the movx instruction, write a data byte to any location within the 512-byte page to be erased. step 7. clear the pswe bit (register psctl). step 8. clear the psee bit (register pscti).
c8051f326/7 64 rev. 1.1 8.1.3. flash write procedure flash bytes are programmed by software with the following sequence: step 1. disable interrupts (recommended). s tep 2. erase the 512-byte flash page containing the target location, as described in section ?8.1.2. flash erase procedure? on page 63. step 3. write the first key code to flkey: 0xa5. step 4. write the second key code to flkey: 0xf1. step 5. set the pswe bit (register psctl). step 6. clear the psee bit (register psctl). step 7. using the movx instruction, write a single data byte to the desired location within the 512- byte sector. step 8. clear the pswe bit (register psctl). steps 3-8 must be repeated for each byte to be written. after flash writes are complete, pswe should be clea red so that movx instructions do not target program memory. table 8.1. flash electrical characteristics parameter conditions min typ max units flash size c8051f326/7 16384* ? ? bytes endurance 20k 100k ? erase/write erase cycle time 25 mhz system clock 10 15 20 ms write cycle time 25 mhz system clock 40 55 70 s *note: 512 bytes at location 0x3e00 to 0x3fff are reserved.
rev. 1.1 65 c8051f326/7 8.2. non-volatile data storage the flash memory can be used for non-volatile data storage as well as program code. this allows data such as calibration coefficients to be calculated and stored at run time. data is written using the movx write instruction and read us ing the movc instruction. note: movx read instructions always target xram. 8.3. security options the cip-51 provides security options to protect the flash memory from inadvertent modification by soft - ware as well as to prevent the viewing of proprietary program code and constants. the program store w rite enable (bit pswe in register psctl) and the program store erase enable (bit psee in register psctl) bits protect the flash memory from accidental modification by software. pswe must be explicitly set to ?1? before software can modify the flash me mory; both pswe and psee must be set to ?1? before software can erase flash memory. additional security features prevent proprietary program code and data constants from being read or altered across the c2 interface. a security lock byte located at the last byte of fl ash user space offers protection of the flash program memory from access (reads, writes, or erases) by unpr otected code or the c2 inte rface. the flash security mechanism allows the user to lock n 512-byte flash pages, starting at page 0 (addresses 0x0000 to 0x 01ff), where n is the 1?s compliment number represented by the security lock byte. see example below. important notes about the flash security: 1. clearing any bit of the lock byte to ?0? w ill lock the flash page containing the lock byte (in addition to the selected pages). 2. locked pages cannot be read, written, or erased via the c2 interface. 3. locked pages cannot be read, written, or eras e d by user firmware executing from unlocked memory space. 4. user firmware executing in a locked page may re ad and write flash memory in any locked or unlocked page excluding the reserved area. 5. user firmware executing in a locked page ma y er ase flash memory in any locked or unlocked page excluding the reserved area and the page containing the lock byte. 6. locked pages can only be unlocked through the c2 interface with a c2 device erase com - mand. 7. if a user firmware flash access attempt is deni e d (per restrictions #3, #4, and #5 above), a flash error system reset will be generated. security lock byte: 11111101b 1 s compliment: 00000010b flash pages locked: 2 addresses locked: 0x0000 to 0x03ff
c8051f326/7 66 rev. 1.1 figure 8.1. flash program memory map and security byte sfr definition 8.1. psctl: program store r/w control access limit set according to the flash security lock byte c8051f326/7 0x0000 0x3dff lock byte reserved 0x3dfe 0x3e00 flash memory organized in 512-byte pages 0x3c00 unlocked flash pages locked when any other flash pages are locked bits7?3: unused: read = 00000b. write = don?t care. bit2: reserved. read = 0b. must write = 0b. bit1: psee: program store erase enable setting this bit (in combination with pswe) a llows an entire page of flash program memory to be erased. if this bit is logic 1 and flash writes are enabled (pswe is logic 1), a write to flash memory using the movx in struction will erase the entire page that contains the loca- tion addressed by the movx instruction. the va lue of the data byte written does not matter. 0: flash program memory erasure disabled. 1: flash program memory erasure enabled. bit0: pswe: program store write enable setting this bit allows writing a byte of data to the flash program memory using the movx write instruction. the flash location should be erased before writing data. 0: writes to flash program memory disabled. 1: writes to flash program memory enabled; the movx write instruction targets flash memory. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? ? ? reserved psee pswe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8f
rev. 1.1 67 c8051f326/7 sfr definition 8.2. flkey: flash lock and key sfr definition 8.3. flscl: flash scale bits7?0: flkey: flash lock and key register write: this register must be writte n to before flash writes or erases can be performed. flash remains locked until this regist er is written to with the following key codes: 0xa5, 0xf1. the timing of the writes does not matter, as long as the codes are written in order. the key codes must be written for each flas h write or erase operation. fl ash will be locked until the next system reset if the wrong codes are written or if a flash operation is attempted before the codes have been written correctly. read: when read, bits 1-0 indicate the current flash lock state. 00: flash is write/erase locked. 01: the first key code has been written (0xa5). 10: flash is unlocked (w rites/erases allowed). 11: flash writes/erases disa bled until the next reset. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb7 bits7: fose: flash one-shot enable this bit enables the flash read one-shot. w hen the flash one-shot disabled, the flash sense amps are enabled for a full clock cycle during flash reads. at system clock frequen- cies below 10 mhz, disabling the flash one-s hot will increase system power consumption. 0: flash one-shot disabled. 1: flash one-shot enabled. bits6?0: reserved. read = 0. must write 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value fose reserved reserved reserved reserved reserved reserved reserved 10000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb6
c8051f326/7 68 rev. 1.1
rev. 1.1 69 c8051f326/7 9. external ram the c8051f326/7 devices include 1280 bytes of on-chip xram. this xram space is split into user ram ( addresses 0x0000?0x03ff) and usb0 fifo space. the usb0 fifo space is only accessible through the usb fifo registers. figure 9.1. external ram memory map 9.1. accessing user xram user xram can be accessed using the external move instruction (movx) and the data pointer (dptr), or using movx indirect addressing mode. if the movx in struction is used with an 8-bit address operand (such as @r1), then the high byte of the 16-bit addr ess is provided by the external memory interface con - trol register (emi0cn as shown in figure 9.1 ). note: the movx inst r uction is also used for writes to the flash memory. see section ?8. flash memory? on page 63 for details. the movx instruction accesses xram by default. for any of the addressing modes, the upper 6 bits of the 16-bit external data memory address word are "don't cares". as a result, the 1024-byte ram is ma pped modulo style over the entire 64k external data memory address range. for example, the xram byte at address 0x0000 is al so at address 0x0400, 0x0800, 0x0c00, 0x1000, etc. xram 1024 bytes 0x0000 0x03ff same 1024 bytes as from 0x0000 to 0x03ff, wrapped on 1k-byte boundaries 0x0400 0xffff usb fifos 256 bytes accessed only through usb fifo registers (inaccessible using the m o vx instruction) accessed with the movx instruction
c8051f326/7 70 rev. 1.1 9.2. accessing usb fifo space the upper 256 bytes of xram fu nctions as usb fifo space. figure 9.2 shows an expanded view of the fifo space and user xram. fifo space is accessed via usb fifo registers; see section ?12.5. fifo management? on page 95 for more information on accessing these fifos. the fifo block operates on the usb clock domain; thus the usb clock must b e active when accessing fifo space. important note: the usb clock must be active when accessing fifo space. figure 9.2. xram memo ry map expanded view sfr definition 9.1. emi0cn: external memory interface control endpoint0 (64 bytes) 0x00 0xbf 0xc0 0xff user xram (1024 bytes) 0x0000 0x03ff endpoint1 usb fifo space (usb clock domain) user xram space (system clock domain) in (64 bytes) out (128 bytes) bits7?3: unused. read = 000000b. write = don?t care. bits2?0: pgsel[1:0]: xr am page select bits. the xram page select bits provide the high byte of the 16-bit external data memory address when using an 8-bit movx command, effectively selecting a 256-byte page of ram. the upper 6-bits are "don't cares", so the 1k address block is repeated modulo over the entire 64k external data memory address space. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - - - pgsel1 pgsel0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xaa
rev. 1.1 71 c8051f326/7 10. oscillators c8051f326/7 devices in clude a programmable in ternal oscillator, an external clock input circuit, a low fre- quency internal oscillator, and a 4x clock multiplier. the internal o scillator can be enabled/disabled and calibrated using the oscicn and oscicl registers, as shown in fi gure 10.1. the low frequency oscilla- tor can be enabled/disabled and calibrated using the osclcn register, as shown in figure 10.3. the sys- tem clock (sysclk) can be derived from the internal oscillator, external clock, low frequency oscillator, or the 4x clock multiplier divided by 2. the usb clock (u sbclk) can be derived from the internal oscillator divided by 2, external clock, or 4x clock multiplier. oscillator electr ical specifications are given in table 10.3 on page 78. figure 10.1. oscillator diagram 10.1. programmable internal oscillator all c8051f326/7 devices include a pr ogrammable internal oscillator that defaults as the system clock after a system reset. the in ternal oscillator period can be adjusted via the oscicl register. on c8051f326/7 devices, oscicl is factory calibrate d to obtain a 12 mhz frequency. electrical specifications for the preci- sion internal oscillator are given in table 10.3 on page 78. note that the system clock may be derived from the programmed internal oscilla tor divided by 1, 2, 4, or 8, as defined by the ifcn bits in register oscicn. the divide value defaults to 8 following a reset. clock multiplier exosc input circuit xtal2 clkmul mulen mulinit mulrdy mulsel1 mulsel0 programmable internal clock generator en oscicl oscicn ioscen ifrdy suspend ifcn1 ifcn0 iosc n x 2 x 2 exosc iosc sysclk exosc iosc / 2 usbclk usbclk1-0 clksel usbclk1 usbclk0 clksel2 clksl1 clksl0 cmos clock osclcn osclen low frequency oscillator osclf en off (0 hz)
c8051f326/7 72 rev. 1.1 10.1.1. adjusting the internal oscillator on c8051f326/7 devices the oscicl reset value is factory calibrated to result in a 12 mhz in ternal oscillator with a 1.5% accu- racy; this frequency is suitable for use as the usb clock (see section ?10.5. system and usb clock selec- tion? on page 76). software may ad just the frequency of th e internal oscillator using the oscicl register. important note: once the internal o scillator frequency has been modified, the internal os cillator may not be used as the usb clock as described in section ?1 0.5. system and usb clock selection? on page 76. the internal oscillator frequency will reset to its orig inal factory-calibrated frequency following any device reset, at which point the oscillator is suitable for use as the usb clock. 10.1.2. internal oscillator suspend mode the internal oscillato r may be placed in suspend mode by writing ?1? to the suspend bit in register oscicn. in suspend mode, the internal oscillator is stopped until a non-idle usb ev ent is detected (sec- tion ?12. universal serial bus cont roller (usb0)? on page 87) or vbus matches the polarity selected by the vbpol bit in register reg0cn (s ection ?5.2. vbus detection? on pa ge 31). note that the usb trans- ceiver must be enabled or in suspend mode for a usb event to be detected. sfr definition 10.1. oscicn: internal os cillator control bit7: ioscen: internal oscillator enable bit. 0: internal osc illator disabled. 1: internal oscillator enabled. bit6: ifrdy: internal oscilla tor frequency ready flag. 0: internal oscillator is not running at prog rammed frequency. 1: internal oscillator is r unning at progra mmed frequency. bit5: suspend: force suspend writing a ?1? to this bit will force the internal oscillator to be stopped. the oscillator will be re- started on the next non-idle usb event (i.e., resume signaling) or vbus interrupt event (see sfr definition 5.1). bits4?2: unused. read = 000b. write = don't care. bits1?0: ifcn1?0: internal osc illator frequency control bits. 00: sysclk derived from intern al oscillator divided by 8. 01: sysclk derived from intern al oscillator divided by 4. 10: sysclk derived from intern al oscillator divided by 2. 11: sysclk derived from internal oscillator divided by 1. r/w r r/w r r/w r/w r/w r/w reset value ioscen ifrdy suspend ? ? ? ifcn1 ifcn0 11000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb2
rev. 1.1 73 c8051f326/7 sfr definition 10.2. oscicl: internal osci llat or calibration bits4?0: osccal: oscillator calibration value these bits determine the in ternal oscillator period. note: if the sum of the re set value of osccal and osccal is greater than 31 or less than 0, then the device will not be capable of producing the desired frequency. note: the contents of this register are undefined when clock recovery is enabled. see section ?12.4. usb clock configuration? on page 94 for details on clock recovery. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? osccal variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb3
c8051f326/7 74 rev. 1.1 10.2. internal low-frequency (l-f) oscillator c8051f326/7 devices include a low-fr equency oscillator. the osclcn regi ster (see sfr definition 10.3) is used to enabled the oscillator. sfr definition 10.3. osclcn: internal l-f oscillator control 10.3. cmos extern al clock input a cmos clock can be used as an external clock inpu t. the cmos clock should be wired to the xtal2 pin (p0.3) as shown in figure 10.1 on page 71. port pins must be configur ed when using the external oscilla- tor circuit. the port i/o crossbar should be configur ed to allow digital inputs be setting inputen (gpi- ocn.6). also, p0.3 should be configured to open dr ain mode. see section ?11. port input/output? on page 79 for more information. bit7: osclen: internal l-f oscillator enable. 0: internal l-f oscillator disabled. 1: internal l-f oscillator enabled. bit6?0: unused. read = 0000000b. write = don?t care. r / wr rrrrrrr e s e t v a l u e osclen ? ? ? ? ? ? ? 0xxxxxxx bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe3
rev. 1.1 75 c8051f326/7 10.4. 4x clock multiplier the 4x clock multiplier allows a 12 mhz oscillator to generate the 48 mhz cl ock required for full speed usb communication (see section ?12.4. usb clock conf iguration? on page 94). a divided version of the multiplier output can also be used as the system cl ock. see section ?10.5. system and usb clock selec- tion? on page 76 for details on system clock and usb clock source selection. the 4x clock multiplier is configured via the clkmul register. the procedure for configuring and enabling the 4x clock multiplie r is as follows: 1. reset the multiplier by writ in g 0x00 to register clkmul. 2. select the multiplier input source via the mulsel bits. 3. enable the multiplier with the mulen bit (clkmul | = 0x80). 4. delay for >5 s. 5. initialize the multip lier w ith the mulinit bit (clkmul | = 0xc0). 6. poll for mulrdy => ?1?. important note: when using an external clock as the in pu t to the 4x clock multiplier, the external source must be stable before the multiplier is initialized. see section ?10. 5. system and usb clock selection? on page 76 for details on clock selection. sfr definition 10.4. clkmul: clock multiplier control bit7: mulen: clock multiplier enable 0: clock multiplier disabled. 1: clock multiplier enabled. bit6: mulinit: clock multiplier initialize this bit should be a ?0? when the clock multiplie r is enabled. once enabled, writing a ?1? to this bit will initialize the clock multiplier. the mu lrdy bit reads ?1? when the clock multiplier is stabilized. bit5: mulrdy: clock multiplier ready this read-only bit indicates th e status of the clock multiplier. 0: clock multiplier not ready. 1: clock multiplier ready (locked). bits4?1: unused. read = 0000b. write = don?t care. bit0: mulsel: clock mu ltiplier input select this bit selects the clock s upplied to the clock multiplier. r/w r/w r r/w r/w r/w r/w r/w reset value mulen mulinit mulrdy ? ? ? ? mulsel 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address 0xb9 mulsel selected clock 0 internal oscillator 1 external clock
c8051f326/7 76 rev. 1.1 10.5. system and us b clock selection the internal oscillator requires little start-up time and may be selected as the system or usb clock immedi- ately following the oscicn write that en ables the internal oscillator. if the external clock is selected as the system or usb clock, then startup times may vary based on the specifications of the external clock. 10.5.1. system clock selection the clksl[2:0] bits in register cl ksel select which osc illator source is used as the system clock. clksl[2:0] must be set to 001b for the system clock to run from the external clock; however the external clock may still clock certain peripher als (timers, uart, usb) when the in ternal oscillator is selected as the system clock. the system clock may be switched on-the-fly between the in ternal oscillator, external clock, low frequency oscillator, and 4x clock multiplier so long as the selected oscillator is enabled and can pro- vide a stable clock. 10.5.2. usb clock selection the usbclk[1:0] bits in register clksel select which oscillator source is used as the usb clock. the usb clock may be derived from the 4x clock multiplier output, internal oscillator divided by 2, or an exter- nal clock. the usb clock source may also be turned off. the usb clock must be 48 mhz when operating usb0 as a full speed function; the usb clock must be 6 mhz when operating usb0 as a low speed function. see figure 10.5 for usb clock selection options. some example usb clock configurations for full and low speed mode are given below: table 10.1. typical usb full sp eed clock settings internal oscillator clock signal input source selection register bit settings usb clock clock multiplier usbclk = 00b clock multiplier input internal oscillator* mulsel = 0b internal oscillator divide by 1 ifcn = 11b external clock clock signal input source selection register bit settings usb clock clock multiplier usbclk = 10b clock multiplier input ext ernal clock mulsel = 1b port i/o 12 mhz cmos clock inputen = 1b (gpi- ocn.6) *note: clock recovery must be enabled for this configuration. table 10.2. typical usb low speed clock settings internal oscillator clock signal input source selection register bit settings usb clock internal oscillator / 2 usbclk = 01b internal oscillator divide by 1 ifcn = 11b external clock clock signal input source selection register bit settings usb clock external clock usbclk = 10b port i/o 6 mhz cmos clock inputen = 1b (gpi- ocn.6)
rev. 1.1 77 c8051f326/7 sfr definition 10.5. clksel: clock select bits7?6: unused. read = 0b. write = don?t care. bits5?4: usbclk1?0: usb clock select these bits select the clock supplied to usb0. when operating usb0 in full-speed mode, the selected clock should be 48 mhz. when operating usb0 in low-speed mode, the selected clock should be 6 mhz. bit3: unused. read = 0b. write = don?t care. bits2?0: clksl1?0: system clock select these bits select the system clock source. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? usbclk ? clksl 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address 0xa9 usbclk selected clock 00 4x clock multiplier 01 internal oscillator / 2 10 external oscillator 11 clock off (0 hz) clksl selected clock 000 internal oscillator (a s determined by the ifcn bits in register oscicn) 001 external clock 010 4x clock multiplier / 2 011 low frequency oscillator 1xx reserved
c8051f326/7 78 rev. 1.1 table 10.3. internal oscillator el ectrical characteristics ?40 to +85 c unless otherwise specified. parameter conditions min typ max units internal high-frequency oscillator internal oscillator frequency reset frequency 11.82 12 12.18 mhz internal oscillator supply cur rent (from vdd) oscicn.7 = 1 ? 574 ? a usb clock frequency 1 full speed mode low speed mode 47.88 5.91 48 6 48.12 6.09 mhz internal low-frequency oscillator (using factory-calibrated settings) internal oscillator frequency ? 88 ? khz internal oscillator supply cur rent (from vdd) 25 oc, vdd = 3.0 v, osclcn.7 = 1 ? 17 ? a power supply sensitivity constant temperature ? ?3 0.1 2 ? %/v temperature sensitivity constant supply ? 20 8 ? ppm/oc notes: 1. appl ies only to external oscillator sources. 2. rep resents mean 1 standard deviation.
rev. 1.1 79 c8051f326/7 11. port input/output on-chip digital resources are available through 15 i/o pins. port pins are organized as shown in figure 11.1 . each of the port pins can be used as general - purpose i/o (gpio). some port pins can be dedicated to special signals such as /sysclk, ua r t tx and rx, and xtal 2 external clock input. all port i/os are 5 v tolerant (refer to figure 11.2 for the port cell circuit). the port i/o cells are configured as either push-pull or open-drain in the port output mode registers (pnmdout, where n = 0,2,3). com - plete electrical spec ifications for por t i/o are given in ta b l e 11.1 on page 85 . figure 11.1. port i/o functional block diagram i/o cell uart /sysclk p2.0 p2.5 p3.0 6 p3.0 p0.0 p0.1 p0.2 i/o cell p0.5 i/o cell i/o cells p0.4 p0.6 p0.7 i/o cell i/o cells (p0.0 - in) mux p0.0 (p0.0 - out) gpiocn.0 p0.4 p0.5 (p0.4 - in) (p0.5 - in) (p0.4 - out) (p0.5 - out) p0.6 p0.7 2 p2.0 p2.5 p0.1 i/o cell p0.2 tmod.3 /int0 i/o cell /int0 p0.3 p0.3 i/o cell xtal2 c2d tmod.3
c8051f326/7 80 rev. 1.1 figure 11.2. port i/o cell block diagram gnd logic 0 port-output push-pull supply supply /weak-pullup (weak) port pad inputen port-input
rev. 1.1 81 c8051f326/7 11.1. port i/o initialization port i/o initialization cons ists of the following steps: step 1. select if the port pin will be used as an output or input. step 2. if output, select the output mode: open-drain or push-pull. step 3. configure the pnmdout and pn latches according to the desired input or output configuration. step 4. select if /sysclk will appear on the p0.0 output and configure gpiocn.0. step 5. enable global inputs (inputen = ?1). port pins can be used as digital inputs or outputs. to config ure a port pin as a digital input, write ?0? to the corresponding bit in register pnmdout, and write ?1? to the corresponding port latch (register pn). when a port pin is read, the actual voltage at the pin is used to determine a logic 0 or logic 1 value; the port latch is write-only. digital output pins can be configured to open-drain or push-pull. in open drain mode (corresponding bit in pnmd out is set to ?0?), the low output driver is turned on when the port latch is a logic 0 and turned off when the port latch is a logic 1. the high output driver is always off, regardless of the port latch setting. in open drain mode, an output port pin becomes a high im pedance input when the port latch is a logic 1. an external pullup resistor is recommended if the pin is intended for use as an output. this mode is useful when interfacing to 5v logic. each port pin has an internal weak pullup that is en ab led when the weakpud bit ?0 ?, the port output mode is configured as open-drain, and the port latch is a logic 1 (pin is a high impedance input). the weak pullup is disabled if the pin is configured to push-pull mode or the port latch is a logic 0 to avoid unnecessary power dissipation. in push-pull mode (cor res ponding bit in pnmdout is set to ?1 ?), one of the output drivers will always remain on. when the port latch is a logic 0, the low outpu t driver is turned on and the high output driver is off. when the port latch is a logic 1, the low output driv er is turned off and the high output driver is turned on. note that in push-pull mo de, the voltage at the port pin will reflect the logic level of the output port latch. this mode cannot be used to drive logic levels higher than vio or vdd. after each port pin is properly configured as an input or output, special signals can be routed to select port pins. special signals incl ude /sysclk on p0.0, xtal2 clock input on p0.3, uart tx on p0.4, and uart rx on p0.5. the /sysclk signal can be routed to p0 .0 by setting gpiocn.0 to ?1 ?. the xtal2 clock input is always routed to p0.3. the uart tx signal is always enabled, and anded with the p0.4 latch. when using the uart, the p0.4 port latches sh ould be logic ?1? to allow the uart to control the tx pin. if the port latch is written ?0? at any time, the tx signal will be forced to a logic 0. when the uart is not used, the value of the tx signal is parked at logic 1 and p0.4 can be used as gpio. important note: setting the inputen bit in gpiocn to ?1? gl obally enables digital inputs. until global inputs are enabled, all port pins on the device remain as output only and cannot be used to sense the logic level on the port pin. inputen must be set to ?1? in order to use uart rx, xtal2, or the /int0 input. 11.2. general purpose port i/o port0, port2, and port3 are accessed through corres ponding special function registers (sfrs) that are both byte addressable and bit addressable. when writi ng to a port, the value written to the sfr is latched to maintain the output data value at each pin. when re ading, the logic levels of the port's input pins are returned if inputen is set to ?1?. the exception to this is the execution of the read-modify-write instruc - tions. the read-modify-write instruct io ns when operating on a port sfr are the following: anl, orl, xrl, jbc, cpl, inc, dec, and djnz. the mov, clr and setb instructions are also read-modify-write when the destination is an individual bit in a port sfr. fo r these instructions, the value of the register (not the pin) is read, modified, and written back to the sfr.
c8051f326/7 82 rev. 1.1 sfr definition 11.1. gpiocn: global po rt i/o contr ol sfr definition 11.2. p0: port0 sfr definition 11.3. p0mdout: port0 output mode bit7: weakpud: port i/o weak pullup disable. 0: weak pullups enabled (except for i/o pins wit h port latches set to logic 0 or are config- ured to push-pull mode). 1: weak pullups disabled. bit6: inputen: global digital input enable. 0: port i/o input path disabled; port pins can be used as outputs only. 1: port i/o input path enabled. bits5?1: unused. read = 00000b. write = don?t care. bit0: sysclk: /sysclk enable 0: /sysclk unavailable at p0.0 pin. p0.0 latch rout ed to p0.0 pin. 1: /sysclk routed to p0.0. p0.0 latch unavailable at p0.0 pin. r / wr / wrrrrrr / wr e s e t v a l u e weakpud inputen ? ???? sysclk 01000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe2 bits7?0: p0.[7:0] write - output appears on i/o pins. 0: logic low output. 1: logic high output (high impedance if corresponding p0mdout.n bit = 0). read - always reads ?0? if inputen = ?0 ?. otherwise, directly reads port pin. 0: p0.n pin is logic low. 1: p0.n pin is logic high. r/w r/w r/w r/w r/w r/w r/w r/w reset value p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0x80 bits7?0: output configuration bits for p0.7-p0.0 (respectively): 0: corresponding p0.n output is open-drain. 1: corresponding p0.n output is push-pull. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa4
rev. 1.1 83 c8051f326/7 sfr definition 11.4. p2: port2 sfr definition 11.5. p2mdout: port2 output mode sfr definition 11.6. p3: port3 bits7?6: unused. read = 00b. write = don?t care. bits5?0: p2.[5:0] write - output appears on i/o pins. 0: logic low output. 1: logic high output (high impedance if corresponding p2mdout.n bit = 0). read - always reads ?0? if inputen = ?0 ?. otherwise, directly reads port pin. 0: p2.n pin is logic low. 1: p2.n pin is logic high. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xa0 bits7?6: unused. read = 00b. write = don?t care. bits5?0: output configuration bit for p2.5?2.0: 0: p2.0 output is open-drain. 1: p2.0 output is push-pull. r/w r/w r/w r/w r/w r/w r/w r/w reset value ?? 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa6 bits7?1: unused. read = 0000000b. write = don?t care. bit0: p3.0 write - output appears on i/o pins. 0: logic low output. 1: logic high output (high impedance if corresponding p3mdout.n bit = 0). read - always reads ?0? if inputen = ?0 ?. otherwise, directly reads port pin. 0: p3.n pin is logic low. 1: p3.n pin is logic high. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? ? ? ? ? p3.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xb0
c8051f326/7 84 rev. 1.1 sfr definition 11.7. p3mdout: port3 output mode bits7?1: unused. read = 0000000b. write = don?t care. bit0: output configuration bit for p3.0: 0: p3.0 output is open-drain. 1: p3.0 output is push-pull. r/w r/w r/w r/w r/w r/w r/w r/w reset value ??????? 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa7
rev. 1.1 85 c8051f326/7 table 11.1. port i/o dc electrical characteristics (c8051f326) vdd = 2.7 to 3.6 v, ?40 to +85 c unless otherwise specified parameter conditions min typ max units vio = 2.7 to 3.6 v output high voltage ioh = ?10 a; port i/o push-pull ioh = ?3 ma; port i/o push-pull ioh = ?10 ma; port i/o push-pull vio ? 0.1 vio ? 0.7 ? ? ? vio ? 0.8 ? ? ? v output low voltage i ol = 10 a iol = 8.5 ma iol = 25 ma ? ? ? ? ? 1.0 0.1 0.6 ? v input high voltage 2.0 ? ? v input low voltage ? ? 0.8 v input leakage current weak pullup off weak pullup on, v in = 0 v ? ? ? 25 1 50 a vio = 1.8 v output high voltage ioh = ?10 a; port i/o push-pull ioh = ?1 ma; port i/o push-pull vio ? 0.1 vio ? 0.4 ? ? ? ? v output low voltage i ol = 10 a iol = 3 ma ? ? ? ? 0.1 0.4 v input high voltage vdd x 0.7 ? ? v input low voltage ? ? vdd x 0.3 v input leakage current weak pullup off weak pullup on, v in = 0 v ? ? ? 6 1 15 a table 11.2. port i/o dc electrical characteristics (c8051f327) vdd = 2.7 to 3.6 v, ?40 to +85 c unless otherwise specified parameter conditions min typ max units output high voltage ioh = ?10 a; port i/o push-pull ioh = ?3 ma; port i/o push-pull ioh = ?10 ma; port i/o push-pull vdd ? 0.1 vdd ? 0.7 ? ? ? vdd ? 0.8 ? ? ? v output low voltage i ol = 10 a iol = 8.5 ma iol = 25 ma ? ? ? ? ? 1.0 0.1 0.6 ? v input high voltage 2.0 ? ? v input low voltage ? ? 0.8 v input leakage current weak pullup off weak pullup on, v in = 0 v ? ? ? 25 1 50 a
c8051f326/7 86 rev. 1.1 n otes :
rev. 1.1 87 c8051f326/7 12. universal serial bus controller (usb0) c8051f326/7 devices include a complete full/low sp eed usb function for usb peripheral implementa - tions*. the usb function controller (usb0) consists of a ser ial interface engine (sie), usb transceiver (including matching resistors and configurable pullup re sistors), 256 byte fifo bl ock, and clock recovery mechanism for crystal-less operation. no external components are required. the usb function controller and transceiver is universal serial bus specification 2.0 compliant. *note: the c8051f326/7 cannot be used as a usb host device. figure 12.1. usb0 block diagram note: this document assumes a comprehensive understanding of the usb protocol. terms and abbreviations used in this document are defined in the u sb specification. we encourage you to review the latest version of the usb specification before proceeding. transceiver serial interface engine (sie) usb fifos (256b ram) d+ d- vdd endpoint0 in/out endpoint1 in out data transfer control cip-51 core usb control, status, and interrupt registers
c8051f326/7 88 rev. 1.1 12.1. endpoint addressing a total of three endpoint pipes are available. the control endpoint (endpoint0) always functions as a bi-directional in/out endpoint. endpoint 1 is implem ented as a 64 byte in pipe and a 128 byte out pipe: 12.2. usb transceiver the usb transceiver is configured via the usb0xcn register shown in figure 12.1 . this configuration includes transceiver enable/disable, pu llup resistor enable/disable, an d device speed selection (full or low speed). when bit speed = ?1?, usb0 operates as a full speed u sb function, and the on-chip pullup resistor (if enabled) appears on th e d+ pin. when bit speed = ?0?, u sb0 operates as a low speed usb function, and the on-chip pullup resistor (if enabled) app ears on the d- pin. bits 4-0 of register usb0xcn can be used for transceiver testing as described in figure 12.1 . the pullup resistor is enabled only when vbus is present (see section ?5.2. vbus detection? on page 31 for details on vbus detection). important note: the usb clock should be active before the transceiver is enabled. table 12.1. endpoint addressing scheme endpoint associated pipes usb protocol address endpoint0 endpoint0 in 0x00 endpoint0 out 0x00 endpoint1 endpoint1 in 0x81 endpoint1 out 0x01
rev. 1.1 89 c8051f326/7 usb register definition 12.1. usb0xcn: usb0 transceiver control bit7: pren: internal pullup resistor enable the location of the pullup resistor (d+ or d-) is determined by the speed bit. 0: internal pullup resistor disabled (device effectively detached from the usb network). 1: internal pullup resistor enabled when vbus is present (device attached to the usb net- work). bit6: phyen: physical layer enable this bit enables/disables the usb0 physical layer transceiver. 0: transceiver disabled (suspend). 1: transceiver enabled (normal). bit5: speed: usb0 speed select this bit selects the usb0 speed. 0: usb0 operates as a low speed device. if ena bled, the internal pullup resistor appears on the d- line. 1: usb0 operates as a full speed device. if en abled, the internal pullup resistor appears on the d+ line. bits4?3: phytst1-0: physical layer test these bits can be used to test the usb0 transceiver. bit2: dfrec: differential receiver the state of this bit indicates the current differential value present on the d+ and d- lines when phyen = ?1?. 0: differential ?0? signaling on the bus. 1: differential ?1? signaling on the bus. bit1: dp: d+ signal status this bit indicates the current logic level of the d+ pin. 0: d+ signal currently at logic 0. 1: d+ signal currently at logic 1. bit0: dn: d- signal status this bit indicates the current logic level of the d- pin. 0: d- signal currently at logic 0. 1: d- signal currently at logic 1. r/w r/w r/w r/w r/w r r r reset value pren phyen speed phytst1 phytst0 dfrec dp dn 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd7 phytst[1:0] mode d+ d? 00b mode 0: normal (non-test mode) x x 01b mode 1: differential ?1? forced 1 0 10b mode 2: differential ?0? forced 0 1 11b mode 3: single-ended ?0? forced 0 0
c8051f326/7 90 rev. 1.1 12.3. usb register access the usb0 controller registers listed in ta b l e 12.2 are accessed through two sfrs: usb0 address (usb0adr) and usb0 dat a (usb0dat). the usb0adr register se lects which usb register is targeted by reads/writes of the usb0dat register. see figure 12.2 . endpoint control/status registers ar e accessed by fir st writing the usb re gister index with the target end - point number. once the target endpoint number is writ te n to the index register, the control/status registers associated with the target endpoint may be a ccessed. see the ?indexed registers? section of ta b l e 12.2 for a list of endpoint control/status registers. important note: the usb clock must be active when accessing usb registers. figure 12.2. usb0 re gister access scheme usb controller fifo access index register endpoint0 control/ status registers endpoint1 control/ status registers common registers interrupt registers 8051 sfrs usb0adr usb0dat
rev. 1.1 91 c8051f326/7 usb register definition 12.2. usb0adr: usb0 indirect address bits7: busy: usb0 register read busy flag this bit is used during indirect usb0 register ac cesses. software should write ?1? to this bit to initiate a read of the usb0 register targeted by the usbad dr bits (usb0adr.[5-0]). the target address and busy bit may be written in the same write to usb0 adr. after busy is set to ?1?, hardware will clear busy when th e targeted register data is ready in the usb0dat register. software should check busy for ?0? before writing to usb0dat. write: 0: no effect. 1: a usb0 indirect register read is initiated at the address specified by the usbaddr bits. read: 0: usb0dat register data is valid. 1: usb0 is busy accessing an indirect register; usb0dat register data is invalid. bit6: autord: usb0 register auto-read flag this bit is used for block fifo reads. 0: busy must be written manually for each usb0 indirect register read. 1: the next indirect register read will automa tically be initiated when software reads usb0dat (usbaddr bits will not be changed). bits5?0: usbaddr: usb0 indi rect register address these bits hold a 6-bit address used to indirect ly access the usb0 core registers. table 12.2 lists the usb0 core registers and their indire ct addresses. reads a nd writes to usb0dat will target the regi ster indicated by the usbaddr bits. r/w r/w r/w r/w r/w r/w r/w r/w reset value busy autord usbaddr 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x96
c8051f326/7 92 rev. 1.1 usb register definition 12.3. usb0dat: usb0 data usb register definition 12.4. index: usb0 endpoint index this sfr is used to indirectly read and write usb0 registers. write procedure: 1. poll for busy (usb0adr.7) => ?0?. 2. load the target usb0 register address into the usbaddr bits in register usb0adr. 3. write data to usb0dat. 4. repeat (step 2 may be skipped when writing to the same usb0 register). read procedure: 1. poll for busy (usb0adr.7) => ?0?. 2. load the target usb0 register address into the usbaddr bits in register usb0adr. 3. write ?1? to the busy bit in register usb0adr (steps 2 and 3 can be performed in the same write). 4. poll for busy (usb0adr.7) => ?0?. 5. read data from usb0dat. 6. repeat from step 2 (step 2 may be skipped when reading the same usb0 register; step 3 may be skipped when the autord bit (usb0adr.6) is logic 1). r/w r/w r/w r/w r/w r/w r/w r/w reset value usb0dat 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x97 bits7?4: unused. read = 0000b. write = don?t care. bits3?0: epsel: endpoint select these bits select which endpoint is target ed when indexed usb0 registers are accessed. r r r r r/w r/w r/w r/w reset value ? ? ? ? epsel 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x0e index target endpoint 0x0 0 0x1 1 0x2?0xf reserved
rev. 1.1 93 c8051f326/7 table 12.2. usb0 controller registers usb register name usb register address description page number interrupt registers in1int 0x02 endpoint0 and endpoint1 in interrupt flags 101 out1int 0x04 endpoint1 out interrupt flag 101 cmint 0x06 common usb interrupt flags 102 in1ie 0x07 endpoint0 and endpoint1 in interrupt enables 102 out1ie 0x09 endpoint1 out interrupt enable 103 cmie 0x0b common usb interrupt enable 103 common registers faddr 0x00 function address 97 power 0x01 power management 99 framel 0x0c frame number low byte 100 frameh 0x0d frame number high byte 100 index 0x0e endpoint index selection 92 clkrec 0x0f clock recovery control 94 fifon 0x20-0x21 endpoints0-1 fifos 96 indexed registers e0csr 0x11 endpoint0 control / status 106 eincsrl endpoint in control / status low byte 110 eincsrh 0x12 endpoint in control / status high byte 111 eoutcsrl 0x14 endpoint out control / status low byte 113 eoutcsrh 0x15 endpoint out control / status high byte 114 e0cnt 0x16 number of received by tes in endpoint0 fifo 107 eoutcntl endpoint out packet count low byte 114 eoutcnth 0x17 endpoint out packet count high byte 114
c8051f326/7 94 rev. 1.1 12.4. usb clock configuration usb0 is capable of communication as a full or low speed usb function. communication speed is selected via the speed bit in sfr usb0xcn. when operati ng as a low speed func tion, the usb0 clock must be 6 mhz. when operating as a full speed fu nction, the usb0 clock must be 48 mhz. clock options a re described in section ?10. oscillators? on page 71 . the usb0 clock is sele cted via sfr clksel (see figure 10.5 on page 77 ). the usb transceiver must be enabled before enabling clock recovery. clock recovery circuitry uses the inco ming usb data stream to adjust the internal oscillato r; this allows the internal oscillator (and 4x clock multiplier) to meet the requirements for usb clock tolerance. clock recovery should be used in the following configurations: when operating usb0 as a low speed function with clock recovery, software must write ?1? to the crlow bit to enable low speed clock recovery. clock recovery is typically no t necessary in low speed mode. single step mode can be used to help the clock reco ve ry circuitry to lock when high noise levels are pres - ent on the usb network. this mode is not requir e d (or recommended) in typical usb environments. usb register definition 12.5. clkrec: clock recovery control communication speed usb clock 4x clock multiplier input full speed 4x clock multip lier internal oscillator low speed internal oscillator/2 n/a bit7: cre: clock recovery enable. this bit enables/disables the usb clock recovery feature. 0: clock recovery disabled. 1: clock recovery enabled. bit6: crssen: clock recovery single step. this bit forces the oscillator calibration into ?single-step? mode during clock recovery. 0: normal calibration mode. 1: single step mode. bit5: crlow: low speed clock recovery mode. this bit must be set to ?1? if clock recovery is used when operating as a low speed usb device. 0: full speed mode. 1: low speed mode. bits4?0: reserved. read = variable. must write = 01001b. r/w r/w r/w r/w r/w r/w r/w r/w reset value cre crssen crlow reserved 00001001 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x0f
rev. 1.1 95 c8051f326/7 12.5. fifo management 256 bytes of on-chip xram are used as fifo space fo r usb0. this fifo space is split between endpoint0 and endpoint1 as shown in figure 12.3 . fifo space allocated for endpoint1 is split into an in and an out endpoint. figure 12.3. usb fifo allocation 12.5.1. fifo split mode the fifo space for endpoint1 is split such that the upper 64 bytes of the fifo space is used by the in endpoint, and the lower 128 bytes is used by the out endpoint. the fifo space for endpoint0 is not split. t he 64 byte fifo space forms a single in or out fifo. endpoint0 can transfer data in one direction at a time . the endpoint direction (i n/out) is determined by the dirsel bit in the corresponding endpoint?s eincsrh register (see figure 12.20 ). 12.5.2. fifo double buffering the endpoint1 fifo can be configured for double-buffe red mode. in this mode, the maximum packet size is halved and the fifo may contain two packets at a time. this mode is only available for endpoint1. dou - ble buffering may be enabled for the in en dpoint and/or the out endpoint. see ta b l e 12.3 for a list of maximum packet sizes for each fifo configuration. table 12.3. fifo configurations endpoint number split mode enabled? maximum in packet size (double buffer disabled / enabled) maximum out packet size (double buffer dis- abled / enabled) 0n / a 6 4 1 y 64 / 32 128 / 64 user xram (1024 bytes) 0x0000 0x03ff usb clock domain system clock domain endpoint0 (64 bytes) 0x00 0xbf 0xc0 0xff endpoint1 in (64 bytes) out (128 bytes) endpoint1 (split in/out) endpoint0 (in/out) control endpoint
c8051f326/7 96 rev. 1.1 12.5.1. fifo access each endpoint fifo is accessed through a correspond ing fifon register. a read of an endpoint fifon register unloads one byte from the fifo; a write of an endpoi nt fifon register loads one byte into the end - point fifo. when an endpoint fifo is configured for s plit mode, a read of the endpoint fifon register unloads one byte from the out endpoint fifo; a write of the endpoint fifon register loads one byte into the in endpoint fifo. usb register definition 12.6. fifon: usb0 endpoint fifo access usb addresses 0x20?0x21 provide access to the 2 pairs of endpoint fifos: writing to the fifo address loads data into the in fifo for the corresponding endpoint. reading from the fifo address unloads data from the out fifo for the corresponding endpoint. r/w r/w r/w r/w r/w r/w r/w r/w reset value fifodata 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x20?0x23 in/out endpoint fifo usb address 0 0x20 1 0x21
rev. 1.1 97 c8051f326/7 12.6. function addressing the faddr register holds the current usb0 function address. software should write the host-assigned 7-bit function address to the faddr register when received as part of a set_address command. a new address written to faddr will not take effect (usb0 will not respond to the new ad dress) until the end of the current transfer (typic ally following the status phase of the set_address command transfer). the update bit (faddr.7) is set to ?1? by hardware when software writes a new address to the faddr regis - ter. hardware clears the update bit when the new address takes effect as described above. usb register definition 12.7. faddr: usb0 function address bit7: update: function address update set to ?1? when software writes the faddr regist er. usb0 clears this bit to ?0? when the new address takes effect. 0: the last address writte n to faddr is in effect. 1: the last address written to faddr is not yet in effect. bits6?0: function address holds the 7-bit function address for usb0. this address should be written by software when the set_address standard device request is received on endpoint0. the new address takes effect when the device request completes. r r/w r/w r/w r/w r/w r/w r/w reset value update function address 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x00
c8051f326/7 98 rev. 1.1 12.7. function configur ation and control the usb register power ( figure 12.8 ) is used to configure and control usb0 at the device level (enable/ disable, reset/suspend/resume handling, etc.). usb reset: the usbrst bit (power.3) is set to ?1? by ha rdware when reset signaling is detected on the bus. upon this dete ction, the following occur: 1. the usb0 address is reset (faddr = 0x00). 2. endpoint fifos are flushed. 3. control/status registers are reset to 0x00 (e0csr, eincsrl, eincsrh, eoutcsrl, eoutcsrh). 4. usb register index is reset to 0x00. 5. all usb interrupts (excluding the suspend interrupt) are enabled and their corresponding flags cleared. 6. a usb reset interrupt is generated if enabled. writing a ?1? to the usbrst bit will generate an asynchronous usb0 reset. all u sb registers are reset to their default values following this asynchronous reset. suspend mode: with suspend detection enabled (susen = ?1?), usb0 will enter suspend mode when suspend signaling is detect ed on the bus. an interrupt will be gene rated if enabled (s usinte = ?1?). the suspend interrupt service routine (isr) should perfor m application-specific conf iguration tasks such as disabling appropriate peripherals and/or configuring clock sources for low power modes. see section ?10. oscillators? on page 71 for more details on internal oscillato r c onfiguration, in cluding the suspend mode feature of the internal oscillator . usb0 exits suspend mode when any of the following occur: (1) resume signaling is detected or gener - ated, (2) reset signaling is detected, or (3) a device or usb r eset occurs. if suspended, the internal oscil - lator will exit suspend mode upon any of the above listed events. resume signaling: usb0 will exit suspend mode if resume signaling is detected on the bus. a resume interrupt will be generated upon detection if enabled (resinte = ?1?). software may force a remote wakeup by writing ?1? to the resume bit (power.2). when forcing a remote wakeup, software should write resume = ?0? to en d resume signaling 10-15 ms after the remote wakeup is initiated (resume = ?1?). iso update: when software writes ?1? to the isoup bit (power.7), th e iso update function is enabled. with iso update enabled, new packe ts written to an iso in endpoint will not be transmitted until a new start-of-frame (sof) is re ceived. if the iso in endpoint receives an in token before a sof, usb0 will transmit a zero-length packet. when isoup = ?1?, iso update is enabled for all iso endpoints. usb enable: usb0 is disabled following a power-on-reset (por). usb0 is enabled by clearing the usbinh bit (power.4). once written to ?0?, the usbinh can only be set to ?1? by one of the following: (1) a power-on-reset (por), or (2) an asynchronous usb0 reset generated by writing ?1? to the usbrst bit (power.3). software should perform all usb0 configu ration before enabling usb0. the configuration sequence should be performed as follows: step 1. select and enable the usb clock source. s tep 2. reset usb0 by writing usbrst= ?1?. step 3. configure and enable the usb transceiver. step 4. perform any usb0 function configuration (interrupts, suspend detect). step 5. enable usb0 by writing usbinh = ?0?.
rev. 1.1 99 c8051f326/7 usb register definition 12.8. power: usb0 power bit7: isoud: iso update this bit affects all in isochronous endpoints. 0: when software writes inprdy = ?1?, usb0 will send the packet when the next in token is received. 1: when software writes inprdy = ?1?, u sb0 will wait for a sof to ken before sending the packet. if an in token is received before a sof token, usb0 will send a zero-length data packet. bits6?5: unused. read = 00b. write = don?t care. bit4: usbinh: usb0 inhibit this bit is set to ?1? following a power-on reset (por) or an asynchronous usb0 reset (see bit3: reset). software sh ould clear this bit after all usb0 and transceiver initialization is complete. software canno t set this bit to ?1?. 0: usb0 enabled. 1: usb0 inhibited. all usb traffic is ignored. bit3: usbrst: reset detect writing ?1? to this bit forces an asynchronous u sb0 reset. reading this bit provides bus reset status information. read: 0: reset signaling is not present on the bus. 1: reset signaling detected on the bus. bit2: resume: force resume software can force resume signaling on the bus to wake usb0 from suspend mode. writing a ?1? to this bit while in suspend mode (susmd = ?1?) forces usb0 to generate resume sig- naling on the bus (a remote wakeup event). software should writ e resume = ?0? after 10 ms to15 ms to end the resume signaling. an interrupt is generated, and hardware clears susmd, when software writes resume = ?0?. bit1: susmd: suspend mode set to ?1? by hardware when usb0 enters suspend mode. cleared by hardware when soft- ware writes resume = ?0? (fo llowing a remote wakeup) or after detection of resume signal- ing on the bus. 0: usb0 not in suspend mode. 1: usb0 in suspend mode. bit0: susen: suspend detection enable 0: suspend detection disabled. usb0 will ignore suspend sign aling on the bus. 1: suspend detection e nabled. usb0 will enter suspend mode if it detects suspend signaling on the bus. r/w r/w r/w r/w r/w r/w r r/w reset value isoud - - usbinh usbrst resume susmd susen 00010000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x01
c8051f326/7 100 rev. 1.1 usb register definition 12.9. framel: usb0 frame number low usb register definition 12.10. frameh: usb0 frame number high bits7?0: frame number low this register contains bits7-0 of the last received frame number. rrrrrrrrr e s e t v a l u e frame number low 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x0c bits7?3: unused. read = 00000b. write = don?t care. bits2?0: frame number high byte this register contains bits10-8 of the last received frame number. rrrrrrrrr e s e t v a l u e ? ? ? ? ? frame number high 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x0d
rev. 1.1 101 c8051f326/7 12.8. interrupts the read-only usb0 interrupt flags are located in the usb registers shown in figure 12.11 through figure 12.13 . the associated interrupt enable bits are located in the usb registers shown in figure 12.14 through figure 12.16 . a usb0 interrupt is generated when any of the u sb interrupt flags is set to ?1?. the usb0 interrupt is enabled via the eie1 sfr (see section ?6.3. interrupt handler? on page 48 ). important note: reading a usb interrupt flag regist er resets all flags in that register to ?0?. usb register definition 12.11. in1int: usb0 in endpoint interrupt usb register definition 12.12. out1int: usb0 out end point interrupt bits7?2: unused. read = 000000b. write = don?t care. bit1: in1: in endpoint 1 interrupt-pending flag this bit is cleared when software reads the in1int register. 0: in endpoint 1 interrupt inactive. 1: in endpoint 1 interrupt active. bit0: ep0: endpoint 0 interrupt-pending flag this bit is cleared when software reads the in1int register. 0: endpoint 0 interrupt inactive. 1: endpoint 0 interrupt active. rrrrrrrrr e s e t v a l u e ? ? ? ? ? ? in1 ep0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x02 bits7?2: unused. read = 000000b. write = don?t care. bit1: out1: out endpoint 1 interrupt-pending flag this bit is cleared when software reads the out1int register. 0: out endpoint 1 interrupt inactive. 1: out endpoint 1 interrupt active. bit0: unused. read = 0. write = don?t care. rrrrrrrrr e s e t v a l u e ??????out1?00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x04
c8051f326/7 102 rev. 1.1 usb register definition 12.13. cmint: usb0 common interrupt usb register definition 12.14. in1ie: usb0 in endpoint interrupt enable bits7?4: unused. read = 0000b. write = don?t care. bit3: sof: start of frame interrupt set by hardware when a sof token is received. this interrupt event is synthesized by hard- ware: an interrupt will be generated when hardware expects to receive a sof event, even if the actual sof signal is missed or corrupted. this bit is cleared when software reads the cmint register. 0: sof interrupt inactive. 1: sof interrupt active. bit2: rstint: reset in terrupt-pending flag set by hardware when reset signaling is detected on the bus. this bit is cleared when software reads the cmint register. 0: reset interrupt inactive. 1: reset inte rrupt active. bit1: rsuint: resume interrupt-pending flag set by hardware when resume signaling is detected on the bus while usb0 is in suspend mode. this bit is cleared when software reads the cmint register. 0: resume inte rrupt inactive. 1: resume interrupt active. bit0: susint: suspend interrupt-pending flag when suspend detection is enabled (bit susen in register power), this bit is set by hard- ware when suspend signaling is detected on the bus. this bit is cleared when software reads the cmint register. 0: suspend interrupt inactive. 1: suspend interrupt active. rrrrrrrrr e s e t v a l u e ? ? ? ? sof rstint rsuint susint 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x06 bits7?2: unused. read = 000000b. write = don?t care. bit1: in1e: in endpoint 1 interrupt enable 0: in endpoint 1 interrupt disabled. 1: in endpoint 1 interrupt enabled. bit0: ep0e: endpoint 0 interrupt enable 0: endpoint 0 interrupt disabled. 1: endpoint 0 interrupt enabled. r/w r/w r/w r/w r/w r/w r/w r/w reset value ??????in1eep0e00000011 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x07
rev. 1.1 103 c8051f326/7 usb register definition 12.15. out1ie: usb0 out endpoint interrupt enable usb register definition 12.16. cmie: usb0 common interrupt enable bits7?2: unused. read = 000000b. write = don?t care. bit1: out1e: out endpoint 1 interrupt enable 0: out endpoint 1 interrupt disabled. 1: out endpoint 1 interrupt enabled. bit0: unused. read = 0. write = don?t? care. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? ? ? ? out1e ? 00000010 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x09 bits7?4: unused. read = 0000b. write = don?t care. bit3: sofe: start of frame interrupt enable 0: sof interrupt disabled. 1: sof interrupt enabled. bit2: rstinte: reset interrupt enable 0: reset interrupt disabled. 1: reset inte rrupt enabled. bit1: rsuinte: resume interrupt enable 0: resume interrupt disabled. 1: resume interrupt enabled. bit0: susinte: suspend interrupt enable 0: suspend interrupt disabled. 1: suspend interrupt enabled. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? ? sofe rstinte rsuinte susinte 00000110 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x0b
c8051f326/7 104 rev. 1.1 12.9. the serial interface engine the serial interface engine (sie) performs all low level usb protocol tasks, interrupting the processor when data has successfully been transmitted or received. when receiv ing data, the sie will interrupt the processor when a complete data packet has been received; appropriate handshaking signals are automat - ically generated by the sie. when tr ansmitting data, the sie will interrupt the processor when a complete data packet has been transmitted and the appropriate handshake signal has been received. the sie will not interrupt the proc essor when corr upted/erroneous packets are received. 12.10. endpoint0 endpoint0 is managed through the usb register e0csr ( figure 12.17 ). the index register must be loaded with 0x00 to access the e0csr register. an endpoint0 interrupt is generated when: 1. a data packet (out or setup) has been received and loaded into the endpoint0 fifo. the oprdy bit (e0csr.0) is set to ?1? by hardware. 2. an in data packet has successfully been unloaded from the endpoint0 fifo and transmitted to the host ; inprdy is re set to ?0? by hardware. 3. an in transaction is completed (this interrupt generated during the status stage of the transac - tion). 4. hardware sets the ststl bit (e0csr.2) after a control transaction ended due to a protocol viola tion. 5. hardware sets the suend bit (e0csr.4) beca use a control transfer ended before firmware sets the dataend bit (e0csr.3). the e0cnt register ( figure 12.18 ) holds the number of received data bytes in the endpoint0 fifo. hardware will automatically detect protocol errors and send a stal l condition in resp onse. firmware may force a stall condition to abort the current transfer. when a stall condition is generated, the ststl bit will be set to ?1? and an interrupt gen erated. the following co nditions will cause hardwa re to generate a stall condition: 1. the host sends an out token during a out data phase after the dataend bit has been set to ?1?. 2. the host sends an in token during an in data phase after the dataend bit has been set to ?1?. 3. the host sends a packet that exceeds the maximum packet size for endpoint0. 4. the host sends a non-zero length data1 packet during the status phase of an in transaction. firmware sets the sdstl bit (e0csr.5) to ?1?. 12.10.1.endpoint0 setup transactions all control transfers must begin with a setup packet. setup packets are similar to out packets, contain - ing an 8-byte data field sent by the host. any setup p acket containing a comma nd field of anything other than 8 bytes will be automatically re jected by usb0. an endpoint0 inte rrupt is generate d when the data from a setup packet is loaded into the endpoint0 fifo. software should unload the command from the endpoint0 fifo, decode the command, perform any necess ary tasks, and set the soprdy bit to indicate that it has serviced the out packet.
rev. 1.1 105 c8051f326/7 12.10.2.endpoint0 in transactions when a setup request is received that requires usb0 to transmit data to the host, one or more in requests will be sent by the host. for the first in tr ansaction, firmware should lo ad an in packet into the endpoint0 fifo, and set the inprdy bit (e0csr.1). an inte rrupt will be generated when an in packet is transmitted successfully. note that no interrupt will be generated if an in requ est is received before firm - ware has loaded a packet into the endpoint0 fifo . if the re quested data exceeds the maximum packet size for endpoint0 (as reported to the host), the data should be split into multiple packets; each packet should be of the maximum packet size excluding the la st (residual) packet. if the requested data is an inte - ger multiple of the maximum packet size for endpoint 0, the last data packet should be a zero-length packet signaling the end of the transfer. firmware should set the dataend bit to ?1? after loading into the endpoint0 fifo the last data packet for a transfer. upon reception of the first in token for a particular contr ol transfer, endpoint0 is said to be in transmit mode. in this mode, only in tokens should be sent by the host to en dpoint0. the suend bit (e0csr.4) is set to ?1? if a setup or out token is rece ived while endpoint0 is in transmit mode. endpoint0 will remain in transmit m ode until any of the following occur: 1. usb0 receives an endpoint0 setup or out token. 2. firmware sends a packet less than the maximum endpoint0 packet size. 3. firmware sends a zero-length packet. firmware should set the dataend bit (e0csr.3) to ?1? when performing (2) and (3) above. the sie will transmit a nak in response to an in token if there is no packet ready in the in fifo (inprdy = ?0?). 12.10.3.endpoint0 out transactions when a setup request is received that requires the host to transmit data to usb0, one or more out requests will be sent by the host. when an out packet is successfully received by usb0, hardware will set the oprdy bit (e0csr.0) to ?1? and generate an endpoint0 interrupt. following this interrupt, firmware should unload the out packet from the endpoint0 fifo and set the soprdy bit (e0csr.6) to ?1?. if the amount of data required for the transfer exceeds the maximum packet size for endpoint0, the data will be split into multiple p ackets. if the requested data is an integer multiple of th e maximum packet size for endpoint0 (as reported to the host), the host will send a zero-length data packet signaling the end of the transfer. upon reception of the first out token for a particular co ntrol transfer, endpoint0 is said to be in receive mode. in this mode, only out tokens should be sent by the host to endpoint0. the suend bit (e0csr.4) is set to ?1? if a setup or in token is received while endpoint0 is in receive mode. endpoint0 will remain in receive mode until: 1. the sie receives a setup or in token. 2. the host sends a packet less than the maximum endpoint0 packet size. 3. the host sends a zero-length packet. firmware should set the dataend bit (e0csr.3) to ?1? when the expected amount of data has been received. the sie will transmit a sta ll condition if the host sends an out packet after the dataend bit has been set by firmware. an interr upt will be genera ted with the ststl bit (e0csr .2) set to ?1? after the stall is transmitted.
c8051f326/7 106 rev. 1.1 usb register definition 12.17. e0csr: usb0 endpoint0 control bit7: ssuend: serviced setup end write: software should set this bit to ?1? afte r servicing a setup end (bit suend) event. hardware clears the suend bit when software writes ?1? to ssuend. read: this bit always reads ?0?. bit6: soprdy: serviced oprdy write: software should write ?1? to this bit after servicing a received endpoint0 packet. the oprdy bit will be cleared by a write of ?1? to soprdy. read: this bit always reads ?0?. bit5: sdstl: send stall software can write ?1? to this bi t to terminate the current transf er (due to an error condition, unexpected transfer request, etc.). hardware will clear th is bit to ?0? when the stall hand- shake is transmitted. bit4: suend: setup end hardware sets this read-only bit to ?1? when a control transaction ends before software has written ?1? to the dataend bit. hardware clears this bit when software writes ?1? to ssu- end. bit3: dataend: data end software should write ?1? to this bit: 1. when writing ?1? to inprdy for the last outgoing data packet. 2. when writing ?1? to inprdy for a zero-length data packet. 3. when writing ?1? to soprdy after se rvicing the last incoming data packet. this bit is automatically cleared by hardware. bit2: ststl: sent stall hardware sets this bit to ?1? after transmitting a stall handshake signal. this flag must be cleared by software. bit1: inprdy: in packet ready software should write ?1? to this bit after l oading a data packet into the endpoint0 fifo for transmit. hardware clear s this bit and generates an interrupt under either of the following conditions: 1. the packet is transmitted. 2. the packet is overwritten by an incoming setup packet. 3. the packet is overwritten by an incoming out packet. bit0: oprdy: out packet ready hardware sets this read-only bit and generat es an interrupt when a data packet has been received. this bit is cleared only when software writes ?1? to the soprdy bit. r/w r/w r/w r r/w r/w r/w r reset value ssuend soprdy sdstl suend dataend ststl inprdy oprdy 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x11
rev. 1.1 107 c8051f326/7 usb register definition 12.18. e0cnt: usb0 end point 0 dat a count bit7: unused. read = 0. write = don?t care. bits6?0: e0cnt: endpoint 0 data count this 7-bit number indicates the number of received data bytes in the endpoint 0 fifo. this number is only valid while bit oprdy is a ?1?. rrrrrrrrr e s e t v a l u e - e0cnt 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x16
c8051f326/7 108 rev. 1.1 12.11. configuring endpoint1 endpoint1 is configured and controlled through a set of control/status registers: in registers eincsrl and eincsrh, and out registers eoutcsrl and eoutcs rh. the endpoint control/status registers are mapped into the usb register address space based on the contents of the index register ( figure 12.4 ). 12.12. controlling endpoint1 in endpoint1 in is managed via usb registers eincsrl and eincsrh. the in endpoint can be used for interrupt, bulk, or isochronous transfers. isochronous (i so) mode is enabled by writing ?1? to the iso bit in register eincsrh. bulk and interrupt transfers are handled identically by hardware. an endpoint1 in interrupt is generate d by any of th e following conditions: 1. an in packet is successfully transferred to the host. 2. software writes ?1? to the flush bit (eincs rl .3) when the target fifo is not empty. 3. hardware generates a stall condition. 12.12.1.endpoint1 in interrupt or bulk mode when the iso bit (eincsrh.6) is logic 0, endpoint1 ope rates in bulk or interrupt mode. once it has been configured to operate in bulk/inte rrupt in mode (typically following an endpoint0 set_interface com - mand), firmware should load an in packet into the en dpoint in fifo and set the inprdy bit (eincsrl.0). upon reception of an in token, hardware will transmit the data, clear the inprdy bit, and generate an interrupt. writing ?1? to inprdy without writin g any dat a to the endpoint fifo w ill cause a zero-length packet to be transmitted upon reception of the next in token. a bulk or interrupt pipe can be shut down (or halted) by writing ?1? to the sdstl bit (eincsrl.4). while sdstl = ?1?, hardware will re s pond to all in requests with a stall condition. each time hardware gener - ates a stall condition, an interr upt will be generated and the ststl bit (eincsrl.5) set to ?1?. the ststl bit must be rese t to ?0? by firmware. hardware will automatically reset inprdy to ?0? when a packet slot is open in the endpoint fifo. if double buffering is enabled for the target endpoint, it is possible for firmware to load two packets into the in fifo at a time. in this case, hardware will reset inprdy to ?0? immediately after firmware loads the first packet into the fifo and sets inprdy to ?1 ?. an interrupt will not be generated in this case ; an interrupt will only be generated when a data packet is transmitted. when firmware writes ?1? to the fcdt bit (eincsrh.3) , the dat a toggle for each in packet will be toggled continuously, regardless of the handshake received from the host. this feature is typically used by inter - rupt endpoints functioning as rate feed back communication for isochron ous endpoints. when fcdt = ?0?, the data toggle bit will only be toggle d when an ack is sent from the host in response to an in packet. 12.12.2.endpoint1 in isochronous mode when the iso bit (eincsrh.6) is set to ?1?, the target endpoint operates in isochronous (iso) mode. once an endpoint has been configured fo r iso in mode, the host will send one in token (dat a request) per frame; the location of data within each frame may vary . therefore, it is recommended that double buffering be enabled when using endpoint1 in as an isochronous endpoint.
rev. 1.1 109 c8051f326/7 hardware will automatically reset inp rdy (eincsrl.0) to ?0? when a pack et slot is open in the endpoint fifo. note that if double buffering is enabled for the endpoint, it is possible for firmware to load two pack - ets into the in fifo at a time. in this case, hardware will reset inprdy to ?0? immediately after firmware loads the first packet into the fifo an d sets inprdy to ?1?. an interrupt will not be generat ed in this case; an interrupt will only be generated when a data packet is transmitted. if there is not a data packet ready in the endpoint fifo when usb0 receives an in token from the host, usb0 will transmit a zero-length data packet and set the undrun bit (eincsrl.2) to ?1?. the iso update feature (see section ?12.7. function configuration and control? on page 98 ) can be use- ful in starting a double bu f fered iso in endpoint. if the host has alre ady set up the iso in pipe (has begun transmitting in tokens) when firmware writes the firs t data packet to the endpoint fifo, the next in token may arrive and the first data packet sent before firmware has written the second (double buffered) data packet to the fifo. the iso update feature ensures th at any data packet written to the endpoint fifo will not be transmitted during the current frame; the packet will only be sent after a sof signal has been received.
c8051f326/7 110 rev. 1.1 usb register definition 12.19. eincsrl: usb0 in end point control low byte bit7: unused. read = 0. write = don?t care. bit6: clrdt: clear data toggle. write: software should write ?1? to this bit to reset the in endpoint data toggle to ?0?. read: this bit always reads ?0?. bit5: ststl: sent stall hardware sets this bit to ?1? when a stall handshake signal is transmitted. the fifo is flushed, and the inprdy bit cleared. this flag must be cleared by software. bit4: sdstl: send stall. software should write ?1? to this bit to generate a stall handshake in response to an in token. software should write ?0? to this bit to terminate the stall signal. this bit has no effect in iso mode. bit3: flush: fifo flush. writing a ?1? to this bit flushes the next packet to be transmitted from the in endpoint fifo. the fifo pointer is reset and the inprdy bit is cleared. if the fifo contains multiple pack- ets, software must write ?1? to flush for each packet. hardware resets the flush bit to ?0? when the fifo flush is complete. bit2: undrun: data underrun. the function of this bit depends on the in endpoint mode: iso: set when a zero-length packet is sent af ter an in token is received while bit inprdy = ?0?. interrupt/bulk: set when a nak is re turned in response to an in token. this bit must be cleared by software. bit1: fifone: fifo not empty. 0: the in endpoint fifo is empty. 1. the in endpoint fifo contains one or more packets. bit0: inprdy: in packet ready. software should write ?1? to this bit after l oading a data packet into the in endpoint fifo. hardware clears inprdy due to any of the following: 1. a data packet is transmitted. 2. double buffering is enabled (dbien = ?1 ?) and there is an open fifo packet slot. 3. if the endpoint is in isochronous mode (iso = ?1 ?) and isoud = ?1?, inprdy will read ?0? until the next sof is received. an interrupt (if enabled) will be generated when hardware clears inprdy as a result of a packet being transmitted. r w r/w r/w r/w r/w r/w r/w reset value ? clrdt ststl sdstl flush undrun fifone inprdy 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x11
rev. 1.1 111 c8051f326/7 usb register definition 12.20. eincsrh: usb0 in end point control high byte bit7: dbien: in endpoint double-buffer enable. 0: double-buffering disabled for the selected in endpoint. 1: double-buffering enabled for the selected in endpoint. bit6: iso: isochronous transfer enable. this bit enables/disables isochronous transfers on the current endpoint. 0: endpoint configured for bulk/interrupt transfers. 1: endpoint configured for isochronous transfers. bit5?4: unused. read = 00b. write = don?t care. bit3: fcdt: force data toggle. 0: endpoint data toggle switches only when an ack is received following a data packet transmission. 1: endpoint data toggle forced to switch after ev ery data packet is transmitted, regardless of ack reception. bits2-0: unused. read = 000b. write = don?t care. r/w r/w r r r/w r r r reset value dbien iso ? ? fcdt ? ? ? 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x12
c8051f326/7 112 rev. 1.1 12.13. controlling endpoint1 out endpoint1 out is managed via usb registers eoutcsrl and eoutcsrh. it can be used for interrupt, bulk, or isochronous transfers. isoc hronous (iso) mode is enabled by writ ing ?1? to the iso bit in register eoutcsrh. bulk and interrupt transfers are handled identically by hardware. an endpoint1 out interrupt may be generated by the following: 1. hardware sets the oprd y bit (ein csrl.0) to ?1?. 2. hardware generates a stall condition. 12.13.1.endpoint1 out interrupt or bulk mode when the iso bit (eoutcsrh.6) is logic 0, endpoint1 operates in bulk or interrupt mode. once it has been configured to operate in bulk/interrup t out mode (typically following an endpoint0 set_interface command), hardware will set the oprdy bit (eoutcsrl.0) to ?1? and generate an interrupt upon reception of an out token and data packet. the number of bytes in the current out data packet (the packet ready to be unloaded from the fifo) is given in the eoutcnth and eoutcntl reg - isters. in response to this interrup t, fir mware should unload the data packet from the out fifo and reset the oprdy bit to ?0?. a bulk or interrupt pipe can be shut down (or halted ) by writing ?1? to the sdstl bit (eoutcsrl.5). while sdstl = ?1?, hardware will respond to all out requests wit h a st all condition. each time hardware gen - erates a stall condition, an interr upt will be generated and the ststl bit (eou tcsrl.6) set to ?1?. the ststl bit must be rese t to ?0? by firmware. hardware will automatically set op rdy when a packet is ready in the out fifo. note that if double buff - ering is enabled for endpoint1, it is poss ible for two packets to be ready in the out fifo at a time. in this case, hardware will se t oprdy to ?1? immediately after firmwa re unloads the first packet and resets oprdy to ?0?. a second interrupt will be generated in this case. 12.13.2.endpoint1 out isochronous mode when the iso bit (eoutcsrh.6) is set to ?1?, endpoi nt1 operates in isochronous (iso) mode. once it has been configured fo r iso out mode, the host will send exactly one data per usb frame; the location of the data packet within each frame may vary, however. becaus e of this, it is recommended that double buffer - ing be enabled when endpoint1 is used in isochronous mode. each time a data packet is received, hardware will l oad the received dat a packe t into the endpoint fifo, set the oprdy bit (eoutcsrl.0) to ?1?, and generate an interrupt (if enabled). firmware would typically use this interrupt to unload the data packet from the endpoint fifo and reset the oprdy bit to ?0?. if a data packet is received when there is no room in the end point fifo, an inte rrupt will be generated and the ovrun bit (eoutcsrl.2) set to ?1?. if usb0 re ceives an iso data packet with a crc error, the data packet will be loaded into the endpoint fifo, oprdy will be set to ?1?, an interrupt (if en abled) will be gen - erated, and the dataerr bit (eoutcsrl.3) will be set to ?1?. software should check the dataerr bit each time a data packet is unloaded from an iso out endpoint fifo.
rev. 1.1 113 c8051f326/7 usb register definition 12.21. eoutcsrl: usb0 out end point control low byte bit7: clrdt: clear data toggle write: software should write ?1? to this bit to reset the out endpoint data toggle to ?0?. read: this bit always reads ?0?. bit6: ststl: sent stall hardware sets this bit to ?1? when a stall handshake signal is transmitted. this flag must be cleared by software. bit5: sdstl: send stall software should write ?1? to this bit to generate a stall handshake. software should write ?0? to this bit to terminate the stall signal. this bit has no effect in iso mode. bit4: flush: fifo flush writing a ?1? to this bit flushes the next packet to be read from the out endpoint fifo. the fifo pointer is reset and the oprdy bit is cl eared. if the fifo contains multiple packets, software must write ?1? to fl ush for each packet. hardware resets the flush bit to ?0? when the fifo flush is complete. bit3: daterr: data error in iso mode, this bit is set by hardware if a received packet has a crc or bit-stuffing error. it is cleared when software clears oprdy. this bit is only valid in iso mode. bit2: ovrun: data overrun this bit is set by hardware when an incoming data packet cannot be loaded into the out endpoint fifo. this bit is only valid in iso mode, and must be cleared by software. 0: no data overrun. 1: a data packet was lost because of a fu ll fifo since this fl ag was last cleared. bit1: fifoful: out fifo full this bit indicates the contents of the out fifo . if double buffering is enabled for the end- point (dbien = ?1?), the fifo is full when the fifo contains two packets. if dbien = ?0?, the fifo is full when the fifo contains one packet. 0: out endpoint fifo is not full. 1: out endpoint fifo is full. bit0: oprdy: out packet ready hardware sets this bit to ?1? an d generates an interrupt when a data packet is available. soft- ware should clear this bit after each data packet is unloaded from the out endpoint fifo. w r/w r/w r/w r r/w r r/w reset value clrdt ststl sdstl flush daterr ovrun fifoful oprdy 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x14
c8051f326/7 114 rev. 1.1 usb register definition 12.22. eoutcsrh: usb0 out endpoint control high byte usb register definition 12.23. eoutcntl: usb0 out end point count low usb register definition 12.24. eoutcnth: usb0 out end point count high bit7: dboen: double-buffer enable 0: double-buffering disabled for the selected out endpoint. 1: double-buffering enabled for the selected out endpoint. bit6: iso: isochronous transfer enable this bit enables/disables isochronous transfers on the current endpoint. 0: endpoint configured for bulk/interrupt transfers. 1: endpoint configured for isochronous transfers. bits5?0: unused. read = 000000b. write = don?t care. r/w r/w r/w r/w r r r r reset value dboeniso??????00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x15 bits7?0: eocl: out endp oint count low byte eocl holds the lower 8-bits of the 10-bit number of data bytes in the last received packet in the current out endpoint fifo. this num ber is only valid while oprdy = ?1?. rrrrrrrrr e s e t v a l u e eocl 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x16 bits7?2: unused. read = 00000b. write = don?t care. bits1?0: eoch: out endpoint count high byte eoch holds the upper 2-bits of the 10-bit number of data bytes in the last received packet in the current out endpoint fifo. this num ber is only valid while oprdy = ?1?. rrrrrrrrr e s e t v a l u e ? ? ? ? ? ? e0ch 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 usb address: 0x17
rev. 1.1 115 c8051f326/7 table 12.4. usb transceiver electri cal characteristics v dd = 3.0 to 3.6 v, ?40 to +85 c unless otherwise specified. parameters symbol conditions min typ max units usb operating current full speed low speed ? ? 5.7 1.5 ? ? ma transmitter output high voltage v oh 2.8 ? v output low voltage v ol ? ? 0.8 v output crossover point v crs 1.3 ? 2.0 v output impedance z drv driving high driving low ? ? 38 38 ? ? w pullup resistance r pu full speed (d+ pullup) low speed (d? pullup) 1.425 ? 1.5 ? 1.575 ? kw output rise time t r low speed full speed 75 4 ? ? 300 20 ns output fall time t f low speed full speed 75 4 ? ? 300 20 ns receiver differential input sensitiv - ity v di | (d+) ? (d?) | 0.2 ? ? v differential input com - mon mode range v cm 0.8 ? 2.5 v input leakage current i l pullups disabled ? <1.0 ? a note: refer to the usb specification for timing diagrams and symbol definitions.
c8051f326/7 116 rev. 1.1
rev. 1.1 117 c8051f326/7 13. uart0 uart0 is an asynchronous, full duplex serial port offeri ng a variety of data formatting options. a dedicated baud rate generator with a 16-bit timer and selectable prescaler is included, which can generate a wide range of baud rates (details in section ?13.1. baud rate generator? on page 118 ). a received data fifo allows uart0 to receive up to three data bytes before data is lost and an overflow occurs. uart0 has six associated sfrs. three are used for the baud rate generator (sbcon0, sbrlh0, and sbrll0 ), two are used for data formatting, control, and status functions (scon0, smod0), and one is used to send and receive data (sbuf0). the single sbuf0 location provides access to both transmit and receive registers. writes to sbuf0 always access the transmit register. reads of sbuf0 always access the buffered receive register; it is not possi ble to read data from the transmit register. with uart0 interrupts enabled, an interrupt is generated each time a transmit is completed (ti0 is set in scon0), or a data byte has been received (ri0 is set in scon0). the uart0 interrupt flags are not cleared by hardware when the cpu vectors to the interr upt service routine. they must be cleared manually by software, allowing software to determine the cause of the uart0 interrupt (transmit complete or receive complete). if additional bytes are available in the receive fifo, the ri0 bit cannot be cleared by software. figure 13.1. uart0 block diagram sbuf0 rx fifo (3 deep) tx logic rx logic write to sbuf0 read of sbuf0 tx0 rx0 smod0 mce0 s0pt1 s0pt0 pe0 s0dl1 s0dl0 xbe0 sbl0 data formatting scon0 ovr0 perr0 ren0 tbx0 rbx0 ti0 ri0 control / status uart0 interrupt timer (16-bit) pre-scaler (1, 4, 12, 48) sysclk sbrlh0 sbrll0 overflow sbcon0 sb0clk sb0run sb0ps1 sb0ps0 en baud rate generator usbclk
c8051f326/7 118 rev. 1.1 13.1. baud rate generator the uart0 baud rate is generated by a dedicated 16-bit timer which runs from eith er the controller?s core clock (sysclk) or the usb clock (usbclk), and has pres caler options of 1, 4, 12, or 48. the timer and prescaler options combined allow for a wide selection of baud rates over many clock frequencies. the baud rate generator is configured using th re e registers: sbcon0, sbrlh0, and sbrll0. the uart0 baud rate generator co ntrol register (sbcon0, sfr definition 13.4 ) enables or disables the baud rate generator, selects the clock source for the baud rate generator, and selects the prescaler value for the timer. the baud rate generator must be enabled for uart0 to func tion. registers sbrlh0 and sbrll0 contain a 16-bit reload value for the dedicated 16-b it timer. the internal timer counts up from the reload value on every clock tick. on timer overflows (0xffff to 0x0000), the timer is reloaded. the baud rate for uart0 is defined in equation 13.1 , where ?brg clock? is the baud rate generator?s selected clock source. for reliable uart operation, it is recommended th at the uart baud rate is not configured for baud rates faster than sysclk/16. equation 13.1. uart0 baud rate a quick reference for typical baud rates and clock frequencies is given in table 13.1 . baud rate brg clock 65536 (sbrlh0:sbrll0) ? () ----------------------------------------------------------- ---------------- 1 2 -- - 1 prescaler ----------- ---------- - =
rev. 1.1 119 c8051f326/7 table 13.1. baud rate generator settings for standard baud rates target baud rate (bps) actual baud rate (bps) baud rate error oscillator divide factor sb1ps[1:0] (prescaler bits) reload value in sbrlh1:sbrll1 brg clock = 12 mhz 230400 230769 0.16% 52 11 0xffe6 115200 115385 0.16% 104 11 0xffcc 57600 57692 0.16% 208 11 0xff98 28800 28846 0.16% 416 11 0xff30 14400 14388 0.08% 834 11 0xfe5f 9600 9600 0.0% 1250 11 0xfd8f 2400 2400 0.0% 5000 11 0xf63c 1200 1200 0.0% 10000 11 0xec78 brg clock = 24 mhz 230400 230769 0.16% 104 11 0xffcc 115200 115385 0.16% 208 11 0xff98 57600 57692 0.16% 416 11 0xff30 28800 28777 0.08% 834 11 0xfe5f 14400 14406 0.04% 1666 11 0xfcbf 9600 9600 0.0% 2500 11 0xfb1e 2400 2400 0.0% 10000 11 0xec78 1200 1200 0.0% 20000 11 0xd8f0 brg clock = 48 mhz 230400 230769 0.16% 208 11 0xff98 115200 115385 0.16% 416 11 0xff30 57600 57554 0.08% 834 11 0xfe5f 28800 28812 0.04% 1666 11 0xfcbf 14400 14397 0.02% 3334 11 0xf97d 9600 9600 0.0% 5000 11 0xf63c 2400 2400 0.0% 20000 11 0xd8f0 1200 1200 0.0% 40000 11 0xb1e0
c8051f326/7 120 rev. 1.1 13.2. data format uart0 has a number of available options for data form atting. data transfers begin with a start bit (logic low), followed by the data bits (sent lsb-first), a parity or extra bit (if selected), and end with one or two stop bits (logic high). the data length is variable between 5 and 8 bits. a parity bit can be appended to the data, and automatically generated and detected by hardware for even, odd, mark, or space parity. the stop bit length is selectable between 1 and 2 bit times, and a multi-processor communication mode is available for implementing networked uart buses. all of the data formatting options can be configured using the smod0 register, shown in sfr definition 13.2 . figure 13.2 shows the timing for a uart0 transaction without parity or an extra bit enabled. figure 13.3 shows the timing for a uart0 transaction with parity enabled (pe0 = 1). figure 13.4 is an example of a uart0 transacti on when the extra bit is enabled (xbe0 = 1). note that the extra bit feature is not availabl e wh en parity is enabled, and the second stop bit is only an option for data lengths of 6, 7, or 8 bits. figure 13.2. uart0 timing wit hout parity or extra bit figure 13.3. uart0 timing with parity figure 13.4. uart0 ti mi ng with extra bit d 1 d 0 d n-2 d n-1 start bit mark stop bit 1 bit times space n bits; n = 5, 6, 7, or 8 stop bit 2 optional (6,7,8 bit data) d 1 d 0 d n-2 d n-1 parity start bit mark stop bit 1 bit times space n bits; n = 5, 6, 7, or 8 stop bit 2 optional (6,7,8 bit data) d 1 d 0 d n-2 d n-1 extra start bit mark stop bit 1 bit times space n bits; n = 5, 6, 7, or 8 stop bit 2 optional (6,7,8 bit data)
rev. 1.1 121 c8051f326/7 13.3. configuration and operation uart0 provides standard asynchronous, full duplex communication. it can operate in a point-to-point serial communications application, or as a node on a multi-processor serial interface. to operate in a point-to-point application, where t here are only two devices on the serial bus, the mce0 bit in smod0 should be cleared to ?0?. for operation as part of a multi-processor communications bus, the mce0 and xbe0 bits should both be set to ?1?. in both types of applications, data is transmitted from the microcon - troller on the tx0 pin, and received on the rx0 pin. th e tx0 and rx0 pins are configured using the cross - bar and the port i/o registers, as detailed in section ?11. port input/output? on page 79. in typical uart communications, the transmit (tx) outp ut of one device is connec ted to the receive (rx) input of the other device, either directly or through a bus transceiver, as shown in figure 13.5 . figure 13.5. typical uart interconnect diagram 13.3.1. data transmission data transmission begins wh en software writes a data byte to th e sbuf0 register. the ti0 transmit inter - rupt flag (scon0.1) will be set at the end of any transmis sion (the be ginning of the stop -bit time). if enabled, an inte rrupt will occur when ti0 is set. if the extra bit function is enabled (xbe0 = ?1?) and the parity function is disabled (pe0 = ?0?), the value of the tbx0 (scon0.3) bit will be sent in the extra bit position. when the parity function is enabled (pe0 = ?1?), hardware will generate the parity bit according to the selected pa rity type (selected with s0pt[1:0]), and append it to the data field. note: when parity is enabled, the extra bit function is not available. 13.3.2. data reception data reception can begin any time after the ren0 receive enable bit (scon0.4) is set to logic 1. after the stop bit is received, the data byte will be stored in th e receive fifo if the following conditions are met: the receive fifo (3 bytes deep) must not be full, and the stop bit(s) must be logic 1. in the event that the receive fifo is full, the incoming byte w ill be lost, and a receive fi fo overrun error will be generated (ovr0 in register sc on0 will be set to logic 1). if the stop bit(s) were logic 0, the incoming data will not be stor ed in the receive fifo. if the reception conditions are met, the data is stored in the receive fifo, and the ri0 flag will be set. note: when mc e0 = ?1?, ri0 will only be set if the extra bit was equal to ?1?. data can be read from the receive fifo by reading the sbuf0 register. the sbuf0 register represents the oldest byte in the fifo. after sbuf0 is read, the next byte in the fifo is loaded into sbuf0, and space is made available in the fifo for another incoming byte. if enabled, an interrupt will occur when ri0 is set. if the extra bit function is enabled (xbe0 = ?1?) and the p arity function is disabled (pe0 = ?0?), the extra bit for the oldest byte in the fifo can be read from th e rbx0 bit (scon0.2). if the extra bit function is not or rs-232 c8051fxxx rs-232 level translator tx rx c8051fxxx rx tx mcu rx tx pc com port
c8051f326/7 122 rev. 1.1 enabled, the value of the stop bit fo r the oldest fifo byte will be pres ented in rbx0. when the parity func - tion is enabled (pe0 = ?1?), hardwa re will check the received p arity bi t against the selected parity type (selected with s0pt[1:0]) wh en receiving data. if a byte with parity error is rece ived, the perr0 flag will be set to ?1?. this flag must be cleared by software. note: when parity is enabled, th e extra bit function is not available. 13.3.3. multiprocessor communications uart0 supports multiprocessor communication between a master processor and one or more slave pro - cessors by special use of the extra data bit. when a master processor wants to transmit to one or more slaves, it fir st sends an address byte to select the target (s). an address byte differs from a data byte in that its extra bit is logic 1; in a data byte, the extra b it is always set to logic 0. setting the mce0 bit (smod0.7) of a slave processor c onfig ures its uart such that when a stop bit is received, the uart will generate an inte rrupt only if the extra bit is logic 1 (rbx0 = 1) signifying an address byte has been rece ived. in the uart interr upt handler, software w ill compare the received address with the slave's own assigned address. if the addres ses match, the slave will clear its mce0 bit to enable interrupts on the reception of the following da ta byte(s). slaves that we ren't addressed leave their mce0 bits set and do not generate interrupts on the rece ption of the following data bytes, thereby ignoring the data. once the entire message is received, the addressed slave resets its mce0 bit to ignore all trans - missions until it receives the next address byte. multiple addresses can be assigned to a single sl ave and /or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissi ons or a protocol can be implemented such that the master/slave role is temporarily re versed to enable half-duplex transmission between the original master and slave(s). figure 13.6. uart multi-processor mode interconnect diagram master device slave device tx rx rx tx slave device rx tx slave device rx tx v+
rev. 1.1 123 c8051f326/7 sfr definition 13.1. scon0: uart0 control bit7: ovr0: receive fifo overrun flag. this bit is used to indicate a receive fifo overrun condition. 0: receive fifo overrun has not occurred. 1: receive fifo overrun has occurred (an incoming character was discarded due to a full fifo). this bit must be cleared to ?0? by software. bit6: perr0: parity error flag. when parity is enabled, this bit is used to indicate that a parity error has occurred. it is set to ?1? when the parity of the oldest byte in the fifo does not match the selected parity type. 0: parity error has not occurred. 1: parity error has occurred. this bit must be cleared to ?0? by software. bit5: unused. read = 1b. write = don?t care. bit4: ren0: receive enable. this bit enables/disables the ua rt receiver. when disabled, by tes can still be read from the receive fifo. 0: uart0 reception disabled. 1: uart0 reception enabled. bit3: tbx0: extra transmission bit. the logic level of this bit will be assigned to the extra transmi ssion bit when xbe0 is set to ?1?. this bit is not used when parity is enabled. bit2: rbx0: extra receive bit. rbx0 is assigned the value of t he extra bit when xbe0 is set to ?1?. if xbe0 is cleared to ?0?, rbx0 will be assigned the logic leve l of the first stop bit. this bit is not valid when parity is enabled. bit1: ti0: transmit interrupt flag. set to a ?1? by hardware after data has been transmitted, at the beginning of the stop bit. when the uart0 interrupt is enabled, setting this bit causes the cpu to vector to the uart0 interrupt service routine. this bit must be cleared manually by software. bit0: ri0: receive interrupt flag. set to ?1? by hardware when a byte of data has been received by uart0 (set at the stop bit sampling time). when the uart0 interrupt is enab led, setting this bit to ?1? causes the cpu to vector to the uart0 interrup t service routine. this bit must be cleared manually by soft- ware. r/w r/w r r/w r/w r/w r/w r/w reset value ovr0 perr0 ? ren0 tbx0 rbx0 ti0 ri0 00100000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0x98
c8051f326/7 124 rev. 1.1 sfr definition 13.2. smod0: uart0 mode bit7: mce0: multiprocessor communication enable. 0: ri will be activated if stop bit(s) are ?1?. 1: ri will be activated if stop bit(s) and extra bit are ?1? (extra bit must be enabled using xbe0). note: this function is not availabl e when hardware parity is enabled. bits6?5: s0pt[1:0]: parity type. 00: odd 01: even 10: mark 11: space bit4: pe0: parity enable. this bit activates hardware pa rity generation and checking. th e parity type is selected by bits s0pt1-0 when parity is enabled. 0: hardware parity is disabled. 1: hardware parity is enabled. bits3?2: s0dl[1:0]: data length. 00: 5-bit data 01: 6-bit data 10: 7-bit data 11: 8-bit data bit1: xbe0: extra bit enable when enabled, the value of tbx0 will be appended to the data field. 0: extra bit disabled. 1: extra bit enabled. bit0: sbl0: stop bit length 0: short - stop bit is active for one bit time (all data field lengths). 1: long - stop bit is active for two bit times (data length = 6, 7, or 8 bits). r/w r/w r/w r/w r/w r/w r/w r/w reset value mce0 s0pt1 s0pt0 pe0 s0dl1 s0dl0 xbe0 sbl0 00001100 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0x9a
rev. 1.1 125 c8051f326/7 sfr definition 13.3. sbuf0: uart0 data buffer sfr definition 13.4. sbcon0: uart0 baud rate generator control bits7?0: sbuf0[7:0]: serial da ta buffer bits 7?0 (msb?lsb) this sfr is used to both send data from the uart and to read received data from the uart0 receive fifo. write: when data is written to sbuf0, it goes to the transmit shift register and is held for serial transmission. writing a byte to sbuf0 initiates the transmission. read: reading sbuf0 retrieves data from the receive fifo. when read, the oldest byte in the receive fifo is returned, and removed from the fifo. up to three bytes may be held in the fifo. if there are ad ditional bytes available in the fifo, the ri0 bi t will remain at logic ?1?, even after being cleared by software. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x99 bit7: sb0clk: baud rate generator clock source. 0: sysclk is used as baud rate generator clock source. 1: usbclk is used as baud rate generator clock source. bit6: sb0run: baud ra te generator enable. 0: baud rate genera tor is disabled. uart0 will not function. 1: baud rate gene rator is enabled. bits5?2: reserved: read = 0000b. must write 0000b. bits1?0: sb0ps[1:0]: baud ra te prescaler select. 00: prescaler = 12 01: prescaler = 4 10: prescaler = 48 11: prescaler = 1 r/w r/w r/w r/w r/w r/w r/w r/w reset value sb0clk sb0run reserved reserved rese rved reserved sb0ps1 sb0ps0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0x91
c8051f326/7 126 rev. 1.1 sfr definition 13.5. sbrlh0: uart0 baud rate generator high byte sfr definition 13.6. sbrll0: uart0 baud rate generator low byte bits7-0: sbrlh0[7:0]: high byte of reload value for uart0 baud rate generator. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x94 bits7-0: sbrll0[7:0]: low byte of reload value for uart0 baud rate generator. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x93
rev. 1.1 127 c8051f326/7 14. timers each mcu includes two 16-bit timers compatible with those found in the standard 8051. these timers can be used to measure time intervals and generate periodic interrupt requests. timer 0 and timer 1 are nearly id entical and have four primary modes of operation. timers 0 and 1 may be clocked by one of four sources, determined by the timer mode select bits (t1m- t0 m) and the clock scale bits (sca1-sca0). the cloc k scale bits define a pre-scaled clock from which timer 0 and/or timer 1 may be clocked (see figure 14.3 for pre-scaled clock selection). timer 0/1 may then be configured to use this pre-sca led c lock signal or the system clock. timers 0 and 1 have a gate mode which allows the timer to run only when an external interrupt is active ( /int0 for timer 0 and /int1 for timer 1. this mode facilitates pulse width measurements on input on p0.2 (timer 0) and low frequency oscillato r calibration when used with timer 1. 14.1. timer 0 and timer 1 operating modes each timer is implemented as a 16-bit register acce ssed as two separate bytes: a low byte (tl0 or tl1) and a high byte (th0 or th1). the timer control register (tcon) is used to enable timer 0 and timer 1 as well as indicate status. timer 0 interrupts can be en abled by setting the et0 bit in the ie register ( section ?6.3.5. interrupt register descriptions? on page 50 ); timer 1 interrupts can be enabled by setting the et1 bit in the ie register ( sfr definition 6.7 ). both timers operate in one of four primary modes selected by set - ting the mode select bits t1m1-t0m0 in the timer mode register (tmod). each timer can be configured in dependently. each operating mode is described below. table 14.1. timer modes timer 0 and timer 1 modes: 13-bit timer 16-bit timer 8-bit timer with auto-reload two 8-bit timers (timer 0 only)
c8051f326/7 128 rev. 1.1 14.1.1. mode 0: 13-bit timer timer 0 and timer 1 operate as 13-bit timers in mo de 0. the following describes the configuration and operation of timer 0. however, both timers operate id entically, and timer 1 is configured in the same man - ner as described for timer 0. the th0 register holds the eight msbs of the 13-bit ti mer . tl0 holds the five lsbs in bit positions tl0.4- tl0.0. the three upper bits of tl0 (tl0.7-tl0.5) ar e indeterminate and should be masked out or ignored when reading. as the 13-bit timer register increments and overflows from 0x1fff (all ones) to 0x0000, the timer overflow flag tf0 (t con.5) is set and an interrupt will occu r if timer 0 interrupts are enabled. setting the tr0 bit (tcon.4) enables the timer when ei the r gate0 (tmod.3) is logic 0 or gate0 is logic 1 and the input signal /int0 is active. setting gate0 to logic 1 allows the timer to be controlled by the external input signal /int0, facilitating pulse width measurements. w hen gate0 is set to logic 1, the /int0 input pin is p0.2. see ta b l e 6.4 on page 49 for detailed information on how gate0 affects /int0 functionality. setting tr0 does not force the timer to re set. the timer registers should be loaded with the desired initial value before the timer is enabled. tl1 and th1 form the 13-bit register for timer 1 in the same manner as described above for tl0 and th0. timer 1 is confi gured and controlled using the relevant tcon and tmod bits just as with timer 0. the inpu t signal /int1 is used with timer 1. see section ?6.3.2. external interrupts? on page 49 for a complete description of /int0 and /int1. figure 14.1. t0 mode 0 block diagram table 14.2. timer 0 operation tr0 gate0 /int0 timer 0 x x disabled 1 0 x enabled 1 1 0 (p0.2 high) disabled 1 1 1 (p0.2 low) enabled x = don't care tclk tl0 (5 bits) th0 (8 bits) tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tr0 0 1 sysclk pre-scaled clock ckcon s c a 0 s c a 1 t 0 m t 1 m tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 gate0 /int0
rev. 1.1 129 c8051f326/7 14.1.2. mode 1: 16-bit timer mode 1 operation is the same as mode 0, except that the timer registers use all 16 bits. the timers are enabled and configured in mode 1 in the same manner as for mode 0. 14.1.3. mode 2: 8-bit timer with auto-reload mode 2 configures timer 0 and timer 1 to operate as 8- bit timers with automatic re load of the start value. tl0 holds the count and th0 holds the reload value. w hen the counter in tl0 overflows from all ones to 0x00, the timer overflow flag tf0 (tco n.5) is set and the counter in tl0 is reloaded from th0. if timer 0 interrupts are enab led, an interrupt will occur wh en the tf0 flag is set. the reload value in th0 is not changed. tl0 must be initialized to the desired value before enabling the timer for the first count to be cor - rect. when in mode 2, timer 1 ope rates identically to timer 0. both timers are enabled and configured in mode 2 in the same manner as mode 0. setting the tr0 bit ( tcon.4) enables the timer when gate0 (tmod.3) is logic 0 or when gate0 is logic 1 and the input sig - nal /int0 is active (see section ?6.3.2. external interrupts? on page 49 for details on the external input sig - nals /int0 and /int1). figure 14.2. t0 mode 2 block diagram tclk tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tl0 (8 bits) reload th0 (8 bits) tr0 0 1 sysclk pre-scaled clock ckcon s c a 0 s c a 1 t 0 m t 1 m tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 gate0 /int0
c8051f326/7 130 rev. 1.1 14.1.4. mode 3: two 8-bit timers (timer 0 only) in mode 3, timer 0 is configured as two separate 8-bit timers held in tl0 and th0. the counter in tl0 is controlled using the timer 0 control/status bits in tcon and tmod: tr0, c/t0, gate0 and tf0. tl0 can use either the system clock or an external input signal as its timebase. the th0 register is restricted to a timer function sourced by the system clock or presca led clock. th0 is enabled using the timer 1 run con - trol bit tr1. th0 sets the timer 1 overflow flag tf1 o n overflow and thus controls the timer 1 interrupt. timer 1 is inactive in mode 3. when timer 0 is operat ing in mode 3, timer 1 can be operated in modes 0, 1 or 2, but cannot set the tf1 flag and generate an interrupt. however, the timer 1 overflow can be used to generate baud rates for the uart. while timer 0 is op erating in mode 3, timer 1 run control is handled through its mode settings. to run timer 1 while timer 0 is in mode 3, set the timer 1 mode as 0, 1, or 2. to disable timer 1, configure it for mode 3. figure 14.3. t0 mode 3 block diagram tl0 (8 bits) tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt interrupt tr1 th0 (8 bits) tr0 0 1 sysclk pre-scaled clock ckcon s c a 0 s c a 1 t 0 m t 1 m tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 gate0 /int0
rev. 1.1 131 c8051f326/7 sfr definition 14.1. tcon: timer control bit7: tf1: timer 1 overflow flag. set by hardware when timer 1 overflows. this flag can be cleared by software but is auto- matically cleared when the cpu vectors to the timer 1 interr upt service routine. 0: no timer 1 overflow detected. 1: timer 1 has overflowed. bit6: tr1: timer 1 run control. 0: timer 1 disabled. 1: timer 1 enabled. bit5: tf0: timer 0 overflow flag. set by hardware when timer 0 overflows. this flag can be cleared by software but is auto- matically cleared when the cpu vectors to the timer 0 interr upt service routine. 0: no timer 0 overflow detected. 1: timer 0 has overflowed. bit4: tr0: timer 0 run control. 0: timer 0 disabled. 1: timer 0 enabled. bit3: ie1: external interrupt 1. this flag is set by hardware when an edge/level of type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external inter- rupt 1 service routine if it1 = 1. when it1 = 0, this flag is set to ?1? when /int1 is active. bit2: it1: interrupt 1 type select. this bit selects whether the configured /int1 interrupt will be edge or level sensitive. 0: /int1 is level triggered. 1: /int1 is edge triggered. bit1: ie0: external interrupt 0. this flag is set by hardware when an edge/level of type defined by it0 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external inter- rupt 0 service routine if it0 = 1. when it0 = 0, this flag is set to ?1? when /int0 is active. bit0: it0: interrupt 0 type select. this bit selects whether the configured /int0 interrupt will be edge or level sensitive. 0: /int0 is level triggered. 1: /int0 is edge triggered. r/w r/w r/w r/w r/w r/w r/w r/w reset value tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00001010 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0x88
c8051f326/7 132 rev. 1.1 sfr definition 14.2. tmod: timer mode bit7: gate1: timer 1 gate control. 0: timer 1 enabled when tr1 = 1 irrespective of /int1 logic level. /int1 is activated when the internal oscillator resu mes from a suspended state. 1: timer 1 enabled only when tr1 = 1 and /int1 is active. /int1 is activated every 2 low frequency oscillator clock cycles. this is a rate of 40khz. bit6: reserved. read = 0b. must write 0b. bits5?4: t1m1-t1m0: timer 1 mode select. these bits select the timer 1 operation mode. bit3: gate0: timer 0 gate control. 0: timer 0 enabled when tr0 = 1 irrespective of /int0 logic level. /int0 input pin is p0.0. 1: timer 0 enabled only when tr0 = 1 and /int0 is active. /int0 input pin is p0.2. bit2: reserved. read = 0b. must write 0b. bits1?0: t0m1-t0m0: timer 0 mode select. these bits select the timer 0 operation mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value gate1 reserved t1m1 t1m0 gate0 reserved t0m1 t0m0 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0x89 t1m1 t1m0 mode 0 0 mode 0: 13-bit timer 0 1 mode 1: 16-bit timer 1 0 mode 2: 8-bit timer with auto-reload 1 1 mode 3: timer 1 inactive t0m1 t0m0 mode 0 0 mode 0: 13-bit timer 0 1 mode 1: 16-bit timer 1 0 mode 2: 8-bit timer with auto-reload 1 1 mode 3: two 8-bit timers
rev. 1.1 133 c8051f326/7 sfr definition 14.3. ckcon: clock control bit7?4: unused. read = 0b. write = don?t care. bit3: t1m: timer 1 clock select. this select the clock sour ce supplied to timer 1. 0: timer 1 uses the clock defined by the prescale bits, sca1-sca0. 1: timer 1 uses the system clock. bit2: t0m: timer 0 clock select. this bit selects the clock so urce supplied to timer 0. 0: timer 0 uses the clock defined by the prescale bits, sca1-sca0. 1: timer 0 uses the system clock. bits1?0: sca1-sca0: time r 0/1 prescale bits. these bits control the division of the clock su pplied to timer 0 and/or timer 1 if configured to use prescaled clock inputs. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? ? t1m t0m sca1 sca0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8e sca1 sca0 prescaled clock 0 0 system clock divided by 12 0 1 system clock divided by 4 1 0 system clock divided by 48 note: external clock divided by 8 is synchronized with the system clock.
c8051f326/7 134 rev. 1.1 sfr definition 14.4. tl0: timer 0 low byte sfr definition 14.5. tl1: timer 1 low byte sfr definition 14.6. th0: timer 0 high byte sfr definition 14.7. th1: timer 1 high byte bits 7?0: tl0: timer 0 low byte. the tl0 register is the low byte of the 16-bit timer 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0x8a bits 7?0: tl1: timer 1 low byte. the tl1 register is the low byte of the 16-bit timer 1. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0x8b bits 7?0: th0: timer 0 high byte. the th0 register is the high byte of the 16-bit timer 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0x8c bits 7?0: th1: timer 1 high byte. the th1 register is the high byte of the 16-bit timer 1. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0x8d
rev. 1.1 135 c8051f326/7 15. c2 interface c8051f326/7 devices include an on-chip silicon laboratories 2- wire (c2) debug inte rface to allow flash programming and in-system debugging with the producti on part installed in the end application. the c2 interface uses a clock sig nal (c2ck) and a bi-directional c2 data signal (c2d) to transfer information between the device and a hos t system. see the c2 interface specificat ion for details on the c2 protocol. 15.1. c2 interface registers the following describes the c2 registers necessary to perform flash programming functions through the c2 interface. all c2 registers are accessed through the c2 interface as described in the c2 interface spec - ification. c2 register definition 15.1. c2add: c2 address c2 register definition 15.2. deviceid: c2 device id bits7?0: the c2add register is accessed via the c2 interface to select the ta rget data register for c2 data read and data write commands. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address description 0x00 selects the device id regi ster for data read instructions 0x01 selects the revision id regi ster for data read instructions 0x02 selects the c2 flash programming control register for data read/write instructions 0xb4 selects the c2 flash programming data register for data read/write instructions this read-only register returns the 8-bit device id: 0x0d (c8051f326/7). reset value 00001001 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
c8051f326/7 136 rev. 1.1 c2 register definition 15.3. revid: c2 revision id c2 register definition 15.4. fpctl: c2 flash programming control c2 register definition 15.5. fpdat: c2 flash programming data this read-only register returns the 8- bit revision id: 0x01 (revision b). reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bits7?0 fpctl: flash programming control register. this register is used to enable flash programming via the c2 interface. to enable c2 flash programming, the following codes must be writte n in order: 0x02, 0x01. note that once c2 flash programming is enabled, a system reset must be issued to resume normal operation. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bits7?0: fpdat: c2 flash programming data register. this register is used to pass flash comma nds, addresses, and data during c2 flash accesses. valid commands are listed below. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 code command 0x06 flash block read 0x07 flash block write 0x08 flash page erase 0x03 device erase
rev. 1.1 137 c8051f326/7 15.2. c2 pin sharing the c2 protocol allows the c2 pins to be shared wi th user functions so that in-system debugging and flash programming may be performed. this is possible because c2 communication is typically performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. in this halted state, the c2 interface can safely ?borrow? th e c2ck (/rst) and c2d (p3.0) pins. in most applica - tions, external resistors are required to isolate c2 inte rface traffic from the user application. a typical isola - tion configuration is shown in figure 15.1 . figure 15.1. typical c2 pin sharing the configuration in figure 15.1 assumes the following: 1. the user input (b) cannot change stat e while the target device is halted. 2. the /rst pin on the target device is used as an input only. additional resistors may be necessary depending on the specific application. c2d c2ck /reset (a) input (b) output (c) c2 interface master c8051f326/7
c8051f326/7 138 rev. 1.1 d ocument c hange l ist revision 0.5 to revision 1.0 ? updated section ?1. system overview? on page 13 and ta b l e 1.1, ?product selection guide,? on page 13. - changed ?-gq? references to ?-gm? ? added figure 1.3. "typical connections for the c8051f326" on page 16 and figure 1.4. "typical con - nections for the c8051f327" on page 16 . ? changed figure 4.5. "typical c8051f327 qfn-28 landing diagram" on page 31 to show ground con - nection on pin 3. ? replaced tbds with values in ta b l e 5.1, ?voltage regulator electr ical s pecifications,? on page 31 . ? replaced tbds with values in ta b l e 7.1, ?reset electrical char acteristics,? on page 62 . ? moved usb active characteristics from ta b l e 3.1, ?global dc electrical characteristics,? on page 24 to ta b l e 12.4, ?usb transceiver electrical characteristics,? on page 115 . ? added port information to figure 11.1. "port i/o functional block diagram" on page 79 . ? added read/write state de script ion to bits 7?6 in sfr definition 11.4. ?p2: port2? on page 83. ? clarified description of read state for bits 7?3 in usb register definition 12.10. ?frameh: usb0 frame number high? on page 100 . ? clarified description of read state for bits 7?2 in usb register definition 12.24. ?eoutcnth: usb0 out endpoint count high? on page 114 . ? standardized descriptions for ?unused? and ?reserved? bits in sfr definitions throughout document. revision 1.0 to revision 1.1 ? updated package and land pattern drawings.
rev. 1.1 139 c8051f326/7 n otes :
c8051f326/7 140 rev. 1.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: mcuinfo@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademark s or registered trademarks of their respective holders the information in this document is believed to be accurate in al l respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no re sponsibility for errors and omissions, and disclaims responsibi lity for any consequen ces resulting from the use of information included herein. additionally, silicon laboratories assume s no responsibility for the fun ction- ing of undescribed features or parameters. silicon laboratories reserves the right to make changes wi thout further notice. sili con laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does silicon laboratories assu me any liability arising out of the applicati on or use of any product or circuit, and specifi cally disclaims any and all liability, including without limitation consequential or incident al damages. silicon laboratories product s are not designed, intended, or authorized for use in applications in tended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a si tuation where personal injury or death may occur. should buyer purchase or use silicon laboratories products for any such unintended or unauthorized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.
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